SLVS885I October   2008  – December 2017 TPS23754 , TPS23754-1 , TPS23756

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      High-Efficiency Converter Using TPS23754
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics: PoE and Control
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  APD
      2. 7.3.2  BLNK
      3. 7.3.3  CLS
      4. 7.3.4  Current Sense (CS)
      5. 7.3.5  Control (CTL)
      6. 7.3.6  Detection and Enable (DEN)
      7. 7.3.7  DT
      8. 7.3.8  Frequency and Synchronization (FRS)
      9. 7.3.9  GATE
      10. 7.3.10 GAT2
      11. 7.3.11 PPD
      12. 7.3.12 RTN, ARTN, COM
      13. 7.3.13 T2P
      14. 7.3.14 VB
      15. 7.3.15 VC
      16. 7.3.16 VDD
      17. 7.3.17 VDD1
      18. 7.3.18 VSS
      19. 7.3.19 PowerPAD
    4. 7.4 Device Functional Modes
      1. 7.4.1 PoE Overview
        1. 7.4.1.1  Threshold Voltages
        2. 7.4.1.2  PoE Start-Up Sequence
        3. 7.4.1.3  Detection
        4. 7.4.1.4  Hardware Classification
        5. 7.4.1.5  Inrush and Start-Up
        6. 7.4.1.6  Maintain Power Signature
        7. 7.4.1.7  Start-Up and Converter Operation
        8. 7.4.1.8  PD Hotswap Operation
        9. 7.4.1.9  Converter Controller Features
        10. 7.4.1.10 Bootstrap Topology
        11. 7.4.1.11 Current Slope Compensation and Current Limit
        12. 7.4.1.12 Blanking – RBLNK
        13. 7.4.1.13 Dead Time
        14. 7.4.1.14 FRS and Synchronization
        15. 7.4.1.15 T2P, Start-Up, and Power Management
        16. 7.4.1.16 Thermal Shutdown
        17. 7.4.1.17 Adapter ORing
        18. 7.4.1.18 PPD ORing Features
        19. 7.4.1.19 Using DEN to Disable PoE
        20. 7.4.1.20 ORing Challenges
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistor, RCLS
        6. 8.2.2.6  Dead Time Resistor, RDT
        7. 8.2.2.7  Switching Transformer Considerations and RVC
        8. 8.2.2.8  Special Switching MOSFET Considerations
        9. 8.2.2.9  Thermal Considerations and OTSD
        10. 8.2.2.10 APD Pin Divider Network, RAPD1, RAPD2
        11. 8.2.2.11 PPD Pin Divider Network, RPPD1, RPPD2
        12. 8.2.2.12 Setting Frequency (RFRS) and Synchronization
        13. 8.2.2.13 Current Slope Compensation
        14. 8.2.2.14 Blanking Period, RBLNK
        15. 8.2.2.15 Estimating Bias Supply Requirements and CVC
        16. 8.2.2.16 T2P Pin Interface
        17. 8.2.2.17 Advanced ORing Techniques
        18. 8.2.2.18 Soft Start
        19. 8.2.2.19 Frequency Dithering for Conducted Emissions Control
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 ESD
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Unless otherwise noted: CS = COM = APD = CTL = RTN = ARTN, GATE and GAT2 float, RFRS= 68.1 kΩ, RBLNK= 249 kΩ, DT = VB, PPD = VSS, T2P open, CVB = CVC = 0.1 μF, RDEN = 24.9 kΩ, RCLS open, 0 V ≤ (VDD, VDD1) ≤ 57 V, 0 V ≤ VC ≤ 18 V, –40°C ≤ TJ ≤ 125°C. Typical specifications are at 25°C.

CONTROLLER SECTION ONLY
[VSS = RTN and VDD = VDD1] or [VSS = RTN = VDD], all voltages referred to [ARTN, COM]

PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VC
VCUV UVLO VC rising ‘754 14.3 15 15.7 V
VC rising ‘756 8.7 9 9.3
VCUVH Hysteresis ‘754 (1) 6.2 6.5 6.8
Hysteresis ‘756 (1) 3.3 3.5 3.7
Operating current VC = 12 V, CTL = VB, RDT = 68.1 kΩ 0.7 0.92 1.2 mA
tST Bootstrap start-up time,
CVC = 22 μF		 TPS23756, VDD1 = 10.2 V, VC(0) = 0 V 50 85 175 ms
TPS23756, VDD1 = 35 V, VC(0) = 0 V 27 45 92
TPS23754, VDD1 = 19.2 V, VC(0) = 0 V 49 81 166
TPS23754, VDD1 = 35 V, VC(0) = 0 V 44 75 158
Start-up current source is IVC TPS23754, VDD1 = 19.2 V, VC = 13.9 V 1.7 3.4 5.5 mA
TPS23756, VDD1 = 10.2 V, VC = 8.6 V 0.44 1.06 1.8
TPS23754, TPS23756, VDD1 = 48 V, VC = 0 V 2.7 4.8 6.8
VB
Voltage 6.5 V ≤ VC ≤ 18 V, 0 ≤ IVB ≤ 5 mA 4.8 5.1 5.25 V
FRS
Switching frequency CTL = VB, measure GATE kHz
RFRS = 68.1 kΩ 227 253 278
DMAX Duty cycle CTL= VB, measure GATE 76% 78% 80%
VSYNC Synchronization Input threshold 2 2.2 2.4 V
CTL
VZDC 0% duty cycle threshold VCTL ↓ until GATE stops 1.3 1.5 1.7 V
Input resistance 70 100 145 kΩ
CS
VCSMAX Maximum threshold voltage VCTL = VB, VCS rising until GATE duty cycle drops 0.5 0.55 0.6 V
VSLOPE Internal slope compensation voltage Peak voltage at maximum duty cycle, referenced to CS 120 155 185 mV
ISL_EX Peak slope compensation current VCTL = VB, ICS at maximum duty cycle 30 42 54 μA
Bias current (sourcing) DC component of ICS 1 2.5 4.3 μA
GATE
Source current VCTL = VB, VC = 12 V, GATE high, pulsed measurement 0.37 0.6 0.95 A
Sink current VCTL = VB, VC = 12 V, GATE low, pulsed measurement 0.7 1 1.4 A
GAT2
Source current VCTL = VB, VC = 12 V, GAT2 high, RDT = 24.9 kΩ, pulsed measurement 0.37 0.6 0.95 A
Sink current VCTL = VB, VC = 12 V, GAT2 low, RDT = 24.9 kΩ, pulsed measurement 0.7 1 1.4 A
APD / PPD
VAPDEN APD threshold voltage VAPD rising 1.43 1.5 1.57 V
VAPDH Hysteresis (1) 0.29 0.31 0.33
VPPDEN PPD threshold voltage VPPD- VVSS rising, UVLO disable 1.45 1.55 1.65 V
VPPDH Hysteresis (1) 0.29 0.31 0.33
VPPD2 VPPD- VVSS rising, Class enable 7.4 8.3 9.2 V
VPPD2H Hysteresis (1) 0.5 0.6 0.7
APD leakage current
(source or sink)		 VC = 12 V, VAPD = VB 1 μA
IPPD PPD sink current VPPD-VSS = 1.5 V 2.5 5 7.5 μA
THERMAL SHUTDOWN
turnon temperature TJ rising 135 145 155 °C
Hysteresis(2) 20 °C
(1) The hysteresis tolerance tracks the rising threshold for a given device.
(2) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product warranty.