SLVS885I October   2008  – December 2017 TPS23754 , TPS23754-1 , TPS23756

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      High-Efficiency Converter Using TPS23754
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics: PoE and Control
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  APD
      2. 7.3.2  BLNK
      3. 7.3.3  CLS
      4. 7.3.4  Current Sense (CS)
      5. 7.3.5  Control (CTL)
      6. 7.3.6  Detection and Enable (DEN)
      7. 7.3.7  DT
      8. 7.3.8  Frequency and Synchronization (FRS)
      9. 7.3.9  GATE
      10. 7.3.10 GAT2
      11. 7.3.11 PPD
      12. 7.3.12 RTN, ARTN, COM
      13. 7.3.13 T2P
      14. 7.3.14 VB
      15. 7.3.15 VC
      16. 7.3.16 VDD
      17. 7.3.17 VDD1
      18. 7.3.18 VSS
      19. 7.3.19 PowerPAD
    4. 7.4 Device Functional Modes
      1. 7.4.1 PoE Overview
        1. 7.4.1.1  Threshold Voltages
        2. 7.4.1.2  PoE Start-Up Sequence
        3. 7.4.1.3  Detection
        4. 7.4.1.4  Hardware Classification
        5. 7.4.1.5  Inrush and Start-Up
        6. 7.4.1.6  Maintain Power Signature
        7. 7.4.1.7  Start-Up and Converter Operation
        8. 7.4.1.8  PD Hotswap Operation
        9. 7.4.1.9  Converter Controller Features
        10. 7.4.1.10 Bootstrap Topology
        11. 7.4.1.11 Current Slope Compensation and Current Limit
        12. 7.4.1.12 Blanking – RBLNK
        13. 7.4.1.13 Dead Time
        14. 7.4.1.14 FRS and Synchronization
        15. 7.4.1.15 T2P, Start-Up, and Power Management
        16. 7.4.1.16 Thermal Shutdown
        17. 7.4.1.17 Adapter ORing
        18. 7.4.1.18 PPD ORing Features
        19. 7.4.1.19 Using DEN to Disable PoE
        20. 7.4.1.20 ORing Challenges
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistor, RCLS
        6. 8.2.2.6  Dead Time Resistor, RDT
        7. 8.2.2.7  Switching Transformer Considerations and RVC
        8. 8.2.2.8  Special Switching MOSFET Considerations
        9. 8.2.2.9  Thermal Considerations and OTSD
        10. 8.2.2.10 APD Pin Divider Network, RAPD1, RAPD2
        11. 8.2.2.11 PPD Pin Divider Network, RPPD1, RPPD2
        12. 8.2.2.12 Setting Frequency (RFRS) and Synchronization
        13. 8.2.2.13 Current Slope Compensation
        14. 8.2.2.14 Blanking Period, RBLNK
        15. 8.2.2.15 Estimating Bias Supply Requirements and CVC
        16. 8.2.2.16 T2P Pin Interface
        17. 8.2.2.17 Advanced ORing Techniques
        18. 8.2.2.18 Soft Start
        19. 8.2.2.19 Frequency Dithering for Conducted Emissions Control
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 ESD
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.16 T2P Pin Interface

The T2P pin is an active low, open-drain output indicating a high-power source is available. An optocoupler is typically used to interface with the T2P pin to signal equipment on the secondary side of the converter of T2P status. Optocoupler current-gain is referred to as current transfer ratio (CTR), which is the ratio of transistor collector current to LED current. To preserve efficiency, TI recommends a high-gain optocoupler ( 250% ≤ CTR ≤ 500%, or 300% ≤ CTR ≤ 600% ) along with a high-impedance (for example, CMOS) receiver. Design of the T2P optocoupler interface can be accomplished as follows:

TPS23754 TPS23754-1 TPS23756 t2p_iface_lvs885.gifFigure 32. T2P Interface
  1. T2P ON characteristic: IT2P = 2 mA minimum, VT2P = 1 V
  2. Let VC = 12 V, VOUT = 5 V, RT2P-OUT = 10 kΩ, VT2P-OUT (low) = 400 mV maximum
    1. TPS23754 TPS23754-1 TPS23756 il_eq18_lvs885.gif
  3. The optocoupler CTR will be needed to determine RT2P. A device with a minimum CTR of 300% at 5-mA LED bias current is selected. CTR will also vary with temperature and LED bias current. The strong variation of CTR with diode current makes this a problem that requires some iteration using the CTR versus IDIODE curve on the optocoupler data sheet.
    1. Using the (normalized) curves, a current of 0.4 to 0.5 mA is required to support the output current at the minimum CTR at 25°C.
      1. Pick an IDIODE. For example one around the desired load current.
      2. Use the optocoupler data sheet curve to determine the effective CTR at this operating current. It is usually necessary to apply the normalized curve value to the minimum specified CTR. It might be necessary to ratio or offset the curve readings to obtain a value that is relative to the current that the CTR is specified at.
      3. If IDIODE × CTRI_DIODE is substantially different from IRT2P_OUT, choose another IDIODE and repeat.
    2. This manufacturer’s curves also indicate a –20% variation of CTR with temperature. The approximate forward voltage of the optocoupler diode is 1.1 V from the data sheet.
      TPS23754 TPS23754-1 TPS23756 il_eq19_lvs885.gif
    3. VFLED ≉ 1.1 V
      TPS23754 TPS23754-1 TPS23756 il_eq20_lvs885.gif
    4. Select a 15.4-kΩ resistor. Even though the minimum CTR and temperature variation were considered, the designer might choose a smaller resistor for a little more margin.