SLVSDW2B December   2018  – November 2020 TPS23755

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC-DC Controller Section
    6. 6.6 Electrical Characteristics: PoE and Control
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  CLS Classification
      2. 7.3.2  DEN Detection and Enable
      3. 7.3.3  Internal Pass MOSFET
      4. 7.3.4  DC-DC Controller Features
        1. 7.3.4.1 VCC, VB and Advanced PWM Startup
        2. 7.3.4.2 CS, Current Slope Compensation and Blanking
        3. 7.3.4.3 COMP, FB, CP and Opto-less Feedback
        4. 7.3.4.4 FRS Frequency Setting and Synchronization
        5. 7.3.4.5 Frequency Dithering for Spread Spectrum Applications
        6. 7.3.4.6 SST and Soft-Start of the Switcher
        7. 7.3.4.7 AUX_V, AUX_D and Secondary Adapter Or'ing
      5. 7.3.5  Internal Switching FET - DRAIN, RSNS, SRF and SRR
      6. 7.3.6  VPD Supply Voltage
      7. 7.3.7  VDD Supply Voltage
      8. 7.3.8  GND
      9. 7.3.9  VSS
      10. 7.3.10 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1 PoE Overview
      2. 7.4.2 Threshold Voltages
      3. 7.4.3 PoE Start-Up Sequence
      4. 7.4.4 Detection
      5. 7.4.5 Hardware Classification
      6. 7.4.6 Maintain Power Signature (MPS)
      7. 7.4.7 Start-Up and Converter Operation
      8. 7.4.8 PD Self-Protection
      9. 7.4.9 Adapter ORing
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistor, RCLS
        6. 8.2.2.6  Bulk Capacitance, CBULK
        7. 8.2.2.7  Output Voltage Feedback Divider, RAUX, R1,R2
        8. 8.2.2.8  Setting Frequency, RFRS
        9. 8.2.2.9  Frequency Dithering, RDTR and CDTR
        10. 8.2.2.10 Bias Voltage, CVB and DVB
        11. 8.2.2.11 Transformer design, T1
        12. 8.2.2.12 Current Sense Resistor, RCS
        13. 8.2.2.13 Current Slope Compensation, RS
        14. 8.2.2.14 Bias Supply Requirements, CCC, DCC
        15. 8.2.2.15 Switching Transformer Considerations, RVCC and CCC2
        16. 8.2.2.16 Primary FET Clamping, RCL, CCL, and DCL
        17. 8.2.2.17 Converter Output Capacitance, COUT
        18. 8.2.2.18 Secondary Output Diode Rectifier, DOUT
        19. 8.2.2.19 Slew rate control, RSRF and RSRR
        20. 8.2.2.20 Shutdown at Low Temperatures, DVDD and CVDD
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • RJJ|23
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-0CFA669D-A8CC-4C99-9034-11A127EA64FE-low.gif Figure 5-1 RJJ Package24-Pin VSONTop View
Table 5-1 Pin Functions
PINI/ODESCRIPTION
NO.NAME
1RSNSOSwitching Power FET source connection. Connect to the external power current sense resistor.
2CPOCP provides the clamp for the primary side regulation loop. Connect this pin to the lower end of the second primary side winding of the transformer.
3GND—Power ground used by the flyback power FET gate driver and CP. Connect to RTN.
4SRRISwitching FET Gate sinking current input, used for EMI control. Connect a resistance from SRR to GND to control the Vds rate of rise.
5SRFISwitching FET Gate sourcing current input, used for EMI control. Connect a resistance from SRF to VB to control the Vds rate of fall.
6VBO5-V bias rail for the switching FET gate driver circuit. For internal use only. Bypass with a 0.1-μF ceramic capacitor and 6.2-V Zener diode to GND pin.
7AUX_DIAuxiliary supply detect, internally pulled-up to approximately 5 V. Pull this pin low, typically through an optocoupler from the secondary side, to step down the output voltage of the DC-DC converter when a secondary side auxiliary supply is connected.
8CSIDC-DC controller current sense input. Connect directly to the external power current sense resistor.
9DTHROUsed for spread spectrum frequency dithering. Connect a capacitor from DTHR to RTN and a resistor from DTHR to FRS. If dithering is not used, short DTHR to VB pin.
10FRSI/OThis pin controls the switching frequency of the DC-DC converter. Tie a resistor from this pin to RTN to set the frequency.
11RTN—RTN is the output of the PoE hotswap and the reference ground for the DC-DC controller.
12VSS—Negative power rail derived from the PoE source.
13VDD—Source of DC-DC converter start-up current. Connect to VPD for most applications.
14VPD—Positive input power rail for PoE interface circuit. Derived from the PoE source. Bypass with a 0.1 µF to VSS and protect with a TVS.
15DENI/OConnect a 24.9-kΩ resistor from DEN to VPD to provide the PoE detection signature. Pulling this pin to VSS during powered operation causes the internal hotswap MOSFET to turn off.
16CLSOConnect a resistor from CLS to VSS to program the classification current.
17NC—No connect pin. Leave open.
18FBIConverter error amplifier inverting (feedback) input. It is typically driven by a voltage divider from the auxiliary winding. Also connect to the COMP compensation network.
19COMPOCompensation output of the DC-DC convertor error amplifier. Connect the compensation networks from this pin to the FB pin to compensate the converter.
20AUX_VOAUX_V works with AUX_D to step down the output voltage setting of the DC-DC converter when an auxiliary supply is detected. Typically connected to FB pin through a resistor which defines the new voltage setting.
21VCCI/ODC/DC converter bias voltage. The internal startup current source and converter bias winding output power this pin. Connect a 1-µF minimum ceramic capacitor to RTN.
23NC—No connect pin. Leave open.
24DRAINODrain connection to the internal switching power MOSFET of the DC/DC controller.
-PAD—The exposed thermal pad must be connected to VSS. A large fill area is required to assist in heat dissipation.
A1-A4ANCHORS—Should be soldered to PCB for mechanical performance. These pins are not connected internally.