SLVSDW2B December   2018  – November 2020 TPS23755

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC-DC Controller Section
    6. 6.6 Electrical Characteristics: PoE and Control
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  CLS Classification
      2. 7.3.2  DEN Detection and Enable
      3. 7.3.3  Internal Pass MOSFET
      4. 7.3.4  DC-DC Controller Features
        1. 7.3.4.1 VCC, VB and Advanced PWM Startup
        2. 7.3.4.2 CS, Current Slope Compensation and Blanking
        3. 7.3.4.3 COMP, FB, CP and Opto-less Feedback
        4. 7.3.4.4 FRS Frequency Setting and Synchronization
        5. 7.3.4.5 Frequency Dithering for Spread Spectrum Applications
        6. 7.3.4.6 SST and Soft-Start of the Switcher
        7. 7.3.4.7 AUX_V, AUX_D and Secondary Adapter Or'ing
      5. 7.3.5  Internal Switching FET - DRAIN, RSNS, SRF and SRR
      6. 7.3.6  VPD Supply Voltage
      7. 7.3.7  VDD Supply Voltage
      8. 7.3.8  GND
      9. 7.3.9  VSS
      10. 7.3.10 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1 PoE Overview
      2. 7.4.2 Threshold Voltages
      3. 7.4.3 PoE Start-Up Sequence
      4. 7.4.4 Detection
      5. 7.4.5 Hardware Classification
      6. 7.4.6 Maintain Power Signature (MPS)
      7. 7.4.7 Start-Up and Converter Operation
      8. 7.4.8 PD Self-Protection
      9. 7.4.9 Adapter ORing
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistor, RCLS
        6. 8.2.2.6  Bulk Capacitance, CBULK
        7. 8.2.2.7  Output Voltage Feedback Divider, RAUX, R1,R2
        8. 8.2.2.8  Setting Frequency, RFRS
        9. 8.2.2.9  Frequency Dithering, RDTR and CDTR
        10. 8.2.2.10 Bias Voltage, CVB and DVB
        11. 8.2.2.11 Transformer design, T1
        12. 8.2.2.12 Current Sense Resistor, RCS
        13. 8.2.2.13 Current Slope Compensation, RS
        14. 8.2.2.14 Bias Supply Requirements, CCC, DCC
        15. 8.2.2.15 Switching Transformer Considerations, RVCC and CCC2
        16. 8.2.2.16 Primary FET Clamping, RCL, CCL, and DCL
        17. 8.2.2.17 Converter Output Capacitance, COUT
        18. 8.2.2.18 Secondary Output Diode Rectifier, DOUT
        19. 8.2.2.19 Slew rate control, RSRF and RSRR
        20. 8.2.2.20 Shutdown at Low Temperatures, DVDD and CVDD
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • RJJ|23
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics: PoE and Control

Unless otherwise noted, VVPD = 48 V; RDEN = 24.9 kΩ; RFRS = 60.4 kΩ; CLS, AUX_V, RSNS and DRAIN open; CS, AUX_D, and GND connected to RTN; SRR connected to GND; SRF, FB and DTHR connected to VB; CVB = 0.1 μF; CCC = 1 μF; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.
Unless otherwise noted, VVPD = VVDD , VVCC = VRTN. All voltages referred to VVSS unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
PD DETECTION (DEN)
Detection bias currentDEN open, VVPD = 10 V, Measure IVPD + IVDD + IDEN + IRTN3.58.313.9µA
IlkgDEN leakage currentVDEN = VVPD = 57 V, Measure IDEN0.15µA
Detection currentMeasure IVPD + IVDD + IDEN + IRTN , VVPD = 1.4 V55.556.360μA
Measure IVPD + IVDD + IDEN + IRTN , VVPD = 10 V400407414.5μA
VPD_DISHotswap disable threshold345V
PD CLASSIFICATION (CLS)
ICLSClassification currentRCLS = 649 Ω13 V ≤ VDD ≤ 21 V, Measure IVPD + IVDD + IDEN + IRTN1.82.142.4mA
RCLS = 121 Ω9.910.611.3
RCLS = 68.1 Ω17.618.619.4
RCLS = 45.3 Ω26.527.929.3
VCL_ONClassification regulator lower thresholdRegulator turns on, VVPD rising10.712.113V
VCL_HYSHysteresis(1)0.61.11.55V
VCU_OFFClassification regulator upper thresholdRegulator turns off, VVPD rising212223V
VCU_HYSHysteresis(1)0.50.771V
IlkgLeakage currentVVPD = 57 V, VCLS = 0 V, VDEN = VVSS, Measure ICLS1μA
RTN (PASS DEVICE)
ON-resistance0.360.68Ω
Current limitVRTN = 1.5 V, pulsed measurement405550800mA
Inrush current limitVRTN = 2 V, VVPD: 0 V → 48 V, pulsed measurement100140220mA
Foldback voltage thresholdVRTN rising1112.313.6V
Foldback deglitch timeVRTN rising to when current limit changes to inrush current limit150387600µs
IlkgLeakage currentVVPD = VRTN = 100 V, VDEN = VVSS40μA
PD INPUT SUPPLY (VPD, VDD)
UVLO_RUndervoltage lockout thresholdVVPD rising34.735.536.7V
UVLO_HHysteresis (1)4.14.54.7V
IVPD_VDDOperating currentVCC open, 40 V ≤ VVPD = VVDD ≤ 57 V, Startup completed, Measure IVPD + IVDD300580µA
Off-state currentRTN, GND and VCC open, VVPD = 30 V, Measure IVPD330
THERMAL SHUTDOWN
Turnoff temperature145159165°C
Hysteresis(2)13°C
(1) The hysteresis tolerance tracks the rising threshold for a given device.
(2) These parameters are provided for reference only.