SLVSDW2B December   2018  – November 2020 TPS23755

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC-DC Controller Section
    6. 6.6 Electrical Characteristics: PoE and Control
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  CLS Classification
      2. 7.3.2  DEN Detection and Enable
      3. 7.3.3  Internal Pass MOSFET
      4. 7.3.4  DC-DC Controller Features
        1. 7.3.4.1 VCC, VB and Advanced PWM Startup
        2. 7.3.4.2 CS, Current Slope Compensation and Blanking
        3. 7.3.4.3 COMP, FB, CP and Opto-less Feedback
        4. 7.3.4.4 FRS Frequency Setting and Synchronization
        5. 7.3.4.5 Frequency Dithering for Spread Spectrum Applications
        6. 7.3.4.6 SST and Soft-Start of the Switcher
        7. 7.3.4.7 AUX_V, AUX_D and Secondary Adapter Or'ing
      5. 7.3.5  Internal Switching FET - DRAIN, RSNS, SRF and SRR
      6. 7.3.6  VPD Supply Voltage
      7. 7.3.7  VDD Supply Voltage
      8. 7.3.8  GND
      9. 7.3.9  VSS
      10. 7.3.10 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1 PoE Overview
      2. 7.4.2 Threshold Voltages
      3. 7.4.3 PoE Start-Up Sequence
      4. 7.4.4 Detection
      5. 7.4.5 Hardware Classification
      6. 7.4.6 Maintain Power Signature (MPS)
      7. 7.4.7 Start-Up and Converter Operation
      8. 7.4.8 PD Self-Protection
      9. 7.4.9 Adapter ORing
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistor, RCLS
        6. 8.2.2.6  Bulk Capacitance, CBULK
        7. 8.2.2.7  Output Voltage Feedback Divider, RAUX, R1,R2
        8. 8.2.2.8  Setting Frequency, RFRS
        9. 8.2.2.9  Frequency Dithering, RDTR and CDTR
        10. 8.2.2.10 Bias Voltage, CVB and DVB
        11. 8.2.2.11 Transformer design, T1
        12. 8.2.2.12 Current Sense Resistor, RCS
        13. 8.2.2.13 Current Slope Compensation, RS
        14. 8.2.2.14 Bias Supply Requirements, CCC, DCC
        15. 8.2.2.15 Switching Transformer Considerations, RVCC and CCC2
        16. 8.2.2.16 Primary FET Clamping, RCL, CCL, and DCL
        17. 8.2.2.17 Converter Output Capacitance, COUT
        18. 8.2.2.18 Secondary Output Diode Rectifier, DOUT
        19. 8.2.2.19 Slew rate control, RSRF and RSRR
        20. 8.2.2.20 Shutdown at Low Temperatures, DVDD and CVDD
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • RJJ|23
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics: DC-DC Controller Section

Unless otherwise noted, VVDD = 48 V; RDEN = 24.9 kΩ; RFRS = 60.4 kΩ; CLS, AUX_V, RSNS and DRAIN open; CS, AUX_D, and GND connected to RTN; SRR connected to GND; SRF, FB and DTHR connected to VB; CVB = 0.1 μF; CCC = 1 μF; 8.5 V ≤ VVCC ≤ 16 V; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise noted. Typical values are at 25°C.
[VVSS = VRTN and VVPD = VVDD] or [VVSS = VRTN = VVPD], all voltages referred to VRTN and VGND unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DC-DC SUPPLY (VCC)
VCUVRUndervoltage lockoutVVCC rising88.258.6V
VCUVFVVCC falling5.856.16.25V
VCUVHHysteresis(1)22.152.5V
IRUNOperating current, converter switchingVVCC = 10 V, VFB = VRTN = VRSNS , DRAIN with 2-kΩ pull up to 95 V2.02.35mA
tSTStart-up time, CCC = 1 μFVDD = 10.2 V, VVCC(0) = 0 V0.51.02.5ms
VDD = 35 V, VVCC(0) = 0 V0.50.801.5ms
VVC_STVCC startup voltageMeasure VVCC during startup, IVCC = 0 mA111315.5V
DC-DC TIMING (FRS)
fSWSwitching frequencyVFB = VRSNS = VRTN, Measure at DRAIN223248273kHz
DMAXDuty cycleVFB = VRSNS = VRTN, Measure at DRAIN75%77.5%80%
VSYNCSynchronizationInput threshold22.22.4V
FREQUENCY DITHERING RAMP GENERATOR (DTHR)
IDTRCHCharging (sourcing) current0.5 V < VDTHR < 1.38 V3 x IFRSµA
47.249.652.1µA
IDTRDCDischarging (sinking) current0.6 V < VDTHR < 1.5 V3 x IFRSµA
47.249.652.1µA
VDTUTDithering upper thresholdVDTHR rising until IDTHR > 01.411.5131.60V
VDTLTDithering lower thresholdVDTHR falling until IDTHR < 00.430.4870.54V
VDTPPDithering pk-pk amplitude1.0051.0261.046V
ERROR AMPLIFIER (FB, COMP)
VREFCFeedback regulation voltage1.7231.751.777V
IFB_LKFB leakage current (source or sink)VFB-RTN = 1.75 V0.5μA
GBWSmall signal unity gain bandwidth0.91.2MHz
AOLOpen loop voltage gain7090dB
VZDC0% duty-cycle thresholdVCOMP falling until DRAIN switching stops1.351.51.65V
ICOMPHCOMP source currentVFB = VRTN , VCOMP = 3 V1mA
ICOMPLCOMP sink currentVFB = VVB , VCOMP = 1.25 V2.16mA
VCOMPHCOMP high voltageVFB = VVB , 15 kΩ from COMP to RTN45V
VCOMPLCOMP low voltageVFB = VVB , 15 kΩ from COMP to VB1.1V
COMP to CS gainΔVCS / ΔVCOMP , 0 V < VCS < 0.5 V0.4750.50.525V/V
SOFT-START
tSSSoft-start period81624ms
tCDCool-down period152026ms
CURRENT SENSE (CS)
VCSMAXMaximum threshold voltageVFB = VRTN, VCS rising0.50.550.6V
tOFFDEL_ILMCurrent limit turnoff delayVCS = 0.65 V254160ns
tOFFDEL_PWPWM comparator turnoff delayVCS = 0.4 V254160
Blanking delayIn addtition to tOFFDEL56.57593.5ns
VSLOPEInternal slope compensation voltagePeak voltage at maximum duty cycle, referred to CS120155185mV
ISL_EXPeak slope compensation currentVFB = VRTN, ICS at maximum duty cycle (ac component)304254μA
Bias currentDC component of CS current-6.7-5-3.3μA
SWITCHING POWER FET (DRAIN, RSNS)
BVDSSPower FET break-down voltage150V
RDS(ON)Power FET on resistance0.771.28Ω
VSDSource-to-drain diode forward voltageIRSNS = 500 mA0.611.1V
SECONDARY SIDE AUXILIARY POWER (AUX_D, AUX_V)
VAUXENAUX_D threshold voltageVAUX_D rising1.722.3V
VAUXHHysteresis (1)0.15V
IpullupAUX_D pullup current70100130µA
VAVLAUX_V output low voltageVAUX_D = VVB , 5 KΩ from AUX_V to VB50mV
THERMAL SHUTDOWN
Turnoff temperature145159165°C
Hysteresis(2)13°C
(1) The hysteresis tolerance tracks the rising threshold for a given device.
(2) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty.