Table 1. Class Resistor Selection

8.3.4.1 External Boost Circuit (Q1, Q2, and R_BLST) Considerations

The IEEE802.3at template bounds the peak PSE output current from 50 A for 10 μs and 1.75 A for 75 ms for a two-pair system. In a nonstandard, four-pair system, these current levels may double. During an overload event, the TPS2379 device will limit current to approximately 1 A and the rest of the current will flow through Q1 and R_BLST. Ignoring the ballast resistor and parasitic impedances, the current through Q1 could be as high as 99 A.

Actual system level behavior will be influenced by the circuit parasitic impedances, diode bridge impedance, contact resistances, external MOSFET resistance, and input voltage droop during the overload event. The impedances act to reduce the peak current as well as drop the voltage across Q1 during the overload event. Evaluate the overload performance of your system and ensure that the selected external MOSFET safe operating area (SOA) is not violated during the output overload. The duration of the overload can be terminated if the input voltage droop to the TPS2379 goes below the UVLO falling threshold (typically 32 V). When UVLO occurs, the internal MOSFET is disabled, GATE goes low and the external MOSFET is disabled. This shortened overload duration is beneficial when evaluating the external MOSFET SOA performance.

Additional limiting and control of the external output overload current can be achieved by using the ballast resistor, R_BLST. R_BLST helps balance the internal and external MOSFET load currents and implements external current limiting through Q2. The load current, IL, divides between the external Q1 and the internal pass MOSFET of the TPS2379 as shown Equation 1.

Equation 1.

R_Q1 is the ON resistance of Q1 and R₂₃₇₉ is the ON resistance of the TPS2379. Q2 can be used to force Q1 to limit its current when the voltage across R_BLST exceeds V_BEON of Q2. For further discussion of these details and additional considerations involving PD classification, see the application report titled Implementing a 60-W End-to-End PoE System (SLVA498).

Table 2. Comparison of Operational Limits

8.4.1.1 Threshold Voltages

The TPS2379 has a number of internal comparators with hysteresis for stable switching between the various states. Figure 20 relates the parameters in the Electrical Characteristics section to the PoE states. The mode labeled Idle between Classification and Operation implies that the DEN, CLS, and RTN pins are all high impedance. The state labeled Mark, which is drawn in dashed lines, is part of the new type 2 hardware class state machine.

Figure 20. Threshold Voltages

8.4.1.2 PoE Start-Up Sequence

The waveforms of Figure 21 demonstrate detection, classification, and start-up from a PSE with type 2 hardware classification. The key waveforms shown are V(VDD-VSS), V(RTN-VSS), and IPI. IEEE 802.3at requires a minimum of two detection levels, two class and mark cycles, and start-up from the second mark event. V_RTN to V_SS falls as the TPS2379 charges C_BULK following application of full voltage. In Figure 21, deassertion of the CDB signal is delayed and used to enable load current as seen in the I_PI waveform.

Figure 21. Start-up

8.4.1.3 Detection

The TPS2379 pulls DEN to V_SS whenever V_(VDD-VSS) is below the lower classification threshold. When the input voltage rises above V_CL-ON, the DEN pin goes to an opendrain condition to conserve power. While in detection, RTN is high impedance, and almost all the internal circuits are disabled. An R_DEN of 24.9 kΩ (±1%), presents the correct signature. It may be a small, low-power resistor because it only sees a stress of about 5 mW. A valid PD detection signature is an incremental resistance ( ΔV/ΔI ) between 23.75 kΩ and 26.25 kΩ at the PI.

The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the parallel combination of RDEN and internal VDD loading. The input diode bridge’s incremental resistance may be hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge resistance is partially compensated by the TPS2379's effective resistance during detection.

The type 2 hardware classification protocol of IEEE 802.3at specifies that a type 2 PSE drops its output voltage into the detection range during the classification sequence. The PD is required to have an incorrect detection signature in this condition, which is referred to as a mark event (see Figure 21). After the first mark event, the TPS2379 will present a signature less than 12 kΩ until it has experienced a V_(VDD-VSS) voltage below the mark reset threshold (V_MSR). This is explained more fully under Hardware Classification.

8.4.1.4 Hardware Classification

Hardware classification allows a PSE to determine a PD’s power requirements before powering, and helps with power management once power is applied. Type 2 hardware classification permits high power PSEs and PDs to determine whether the connected device can support high-power operation. A type 2 PD presents class 4 in hardware to indicate that it is a high-power device. A type 1 PSE will treat a class 4 device like a class 0 device, allotting 13 W if it chooses to power the PD. A PD that receives a 2-event class understands that it is powered from a high-power PSE and it may draw up to 25.5 W immediately after the 80 ms start-up period completes. A type 2 PD that does not receive a 2-event hardware classification may choose to not start, or must start in a 13 W condition and request more power through the DLL after start-up. The standard requires a type 2 PD to indicate that it is underpowered if this occurs. Start-up of a high-power PD under 13 W implicitly requires some form of powering down sections of the application circuits.

The maximum power entries in Table 1 determine the class the PD must advertise. The PSE may disconnect a PD if it draws more than its stated Class power, which may be the hardware class or a lower DLL-derived power level. The standard permits the PD to draw limited current peaks that increase the instantaneous power above the Table 1 limit, however the average power requirement always applies.

The TPS2379 implements two-event classification. Selecting an RCLS of 63.4 Ω provides a valid type 2 signature. TPS2379 may be used as a compatible type 1 device simply by programming class 0–3 per Table 1. DLL communication is implemented by the Ethernet communication system in the PD and is not implemented by the TPS2379.

The TPS2379 disables classification above V_{CU_OFF} to avoid excessive power dissipation. CLS voltage is turned off during PD thermal limiting or when DEN is active. The CLS output is inherently current-limited, but should not be shorted to V_SS for long periods of time.

Figure 22 shows how classification works for the TPS2379. Transition from state-to-state occurs when comparator thresholds are crossed (see Figure 19 and Figure 20). These comparators have hysteresis, which adds inherent memory to the machine. Operation begins at idle (unpowered by PSE) and proceeds with increasing voltage from left to right. A 2-event classification follows the (heavy lined) path towards the bottom, ending up with a latched type 2 decode along the lower branch that is highlighted. This state results in a low T2P during normal operation. Once the valid path to type 2 PSE detection is broken, the input voltage must transition below the mark reset threshold to start anew.

Figure 22. Two-Event Class Internal States

8.4.1.5 Inrush and Start-up

IEEE 802.3at has a start-up current and time limitation, providing type 2 PSE compatibility for type 1 PDs. A type 2 PSE limits output current to between 400 mA and 450 mA for up to 75 ms after power up (applying “48 V” to the PI) to mirror type 1 PSE functionality. The type 2 PSE will support higher output current after 75 ms. The TPS2379 implements a 140 mA inrush current, which is compatible with all PSE types. A high-power PD must limit its converter start-up peak current. The operational current cannot exceed 400 mA for a period of 80 ms or longer. This requirement implicitly requires some form of powering down sections of the application circuits.

8.4.1.6 Maintain Power Signature

The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating voltage is applied. A valid MPS consists of a minimum DC current of 10 mA (or a 10 mA pulsed current for at least 75 ms every 325 ms) and an AC impedance lower than 26.3 kΩ in parallel with 0.05 μF. The AC impedance is usually accomplished by the minimum operating C_BULK requirement of 5 μF. When DEN is used to force the hotswap switch off, the DC MPS will not be met. A PSE that monitors the DC MPS will remove power from the PD when this occurs. A PSE that monitors only the ac MPS may remove power from the PD.

8.4.1.7 Start-up and Operation

The internal PoE UVLO (Under Voltage Lock Out) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the downstream converter circuits from loading the PoE input during detection and classification. The converter circuits will discharge C_BULK while the PD is unpowered. Thus V_(VDD-RTN) will be a small voltage just after full voltage is applied to the PD, as seen in Figure 21. The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When V_VDD rises above the UVLO turnon threshold (V_UVLO-R, approximately 38 V) with RTN high, the TPS2379 enables the hotswap MOSFET with an approximate 140 mA (inrush) current limit as seen in Figure 23. The CDB pin is active while C_BULK charges and V_RTN falls from V_VDD to nearly _VVSS. Once the inrush current falls about 10% below the inrush current limit, the PD current limit switches to the operational level (approximately 1000 mA) and CDB is deasserted to allow downstream converter circuitry to start. The TPS2379 asserts GATE after inrush is complete to enable an external pass MOSFET if used. In Figure 23, T2P is active because a type 2 PSE is plugged in.

Figure 23. Power Up and Start

8.4.1.8 PD Hotswap Operation

IEEE 802.3at has taken a new approach to PSE output limiting. A type 2 PSE must meet an output current versus time template with specified minimum and maximum sourcing boundaries. The peak output current may be as high as 50 A for 10 μs or 1.75 A for 75 ms. This makes robust protection of the PD device even more important than it was in IEEE 802.3-2008.

The internal hotswap MOSFET is protected against output faults and input voltage steps with a current limit and deglitched (time-delay filtered) foldback. An overload on the pass MOSFET engages the current limit, with V_RTN-V_VSS rising as a result. GATE is pulled down about 300 μs after RTN current reaches the current limit level. If V_RTN rises above approximately 12 V for longer than about 800 μs, the current limit reverts to the inrush value. The 800 μs deglitch feature prevents momentary transients from causing a PD reset, provided that recovery lies within the bounds of the hotswap and PSE protection. Figure 24 shows an example of the RTN current profile during VDD to RTN short circuit when only the internal hotswap MOSFET is used. The hotswap MOSFET goes into current limit, causing the RTN voltage to increase. Once V_RTN exceeds 12V, I_RTN which was clamped to the current limit drops to the level of inrush current limit after 800µs.

Figure 24. Response to PD Output Short Circuit Without AUX MOSFET

Figure 25 shows an example of the RTN current profile during VDD to RTN short circuit when the external MOSFET is used. The circuit is depicted in Figure 26. The current will divide between the internal and external MOSFETs. During the short circuit, the hotswap MOSFET goes into current limit, causing the RTN voltage to increase. When the internal MOSFET exceeds current limit for about 300 µs, GATE will deassert and shut off the auxiliary MOSFET. V_RTN will rise quickly and the internal MOSFET will go into current limit for approximately 800 µs (after VRTN > about 12 V) and then I_RTN which was clamped to the current limit drops into the inrush current limit.

Figure 25. Response to PD Output Short Circuit With AUX MOSFET

The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like start-up or operation into a V_DD -to-RTN short cause high power dissipation in the MOSFET. An over-temperature shutdown (OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The hotswap MOSFET will be re-enabled with the inrush current limit when exiting from an over-temperature event. Pulling DEN to V_SS during powered operation causes the internal hotswap MOSFET to turn off.

The hotswap switch will be forced off under the following conditions:

1. V_{(DEN –VSS)} < V_{PD_DIS} when V_VDD – V_VSS is in the operational range,
2. PD is over-temperature, or
3. V_{(DEN – VSS)} PoE UVLO falling threshold (about 32 V).

8.4.1.9 CDB and T2P

CDB (converter disable) is an active-low pin that indicates when the internal hotswap MOSFET is inrush limiting. CDB deasserts when inrush is over and can be used to enable a downstream converter to start up. Common interfaces to the converter controller include the soft start or enable pins.

T2P (type 2 PSE) is an active-low multifunction pin that indicates if (PSE = Type_2) and (PD current limit ≠ Inrush).

The usage of T2P is demonstrated in Figure 18. When PSE applies and PD observes a type 2 hardware classification, T2P pin is pulled to RTN as a indication of the type of PSE.

8.4.1.10 Auxiliary Pass MOSFET Control

The TPS2379 can be used in non-standard applications requiring power significantly above the IEEE802.3at, type 2 levels. This implementation can be achieved by utilizing all four Ethernet wire pairs and boosting the TPS2379 hotswap MOSFET operating current limit. Boosting the TPS2379 operating current limit is achieved by adding an external pass MOSFET to share the total load current with the internal hotswap MOSFET. The external pass MOSFET is enabled by the GATE pin after the internal hotswap MOSFET inrush is complete. The GATE pin will deassert if the TPS2379 internal current limit is exceeded in excess of 300 µs.

A comprehensive high power POE design example is discussed in application report Implementing a 60-W, End-to-End PoE System (SLVA498).

8.4.1.11 Using DEN to Disable PoE

The DEN pin may be used to turn the PoE hotswap switch off by pulling it to VSS while in the operational state, or to prevent detection when in the idle state. A low voltage on DEN forces the hotswap MOSFET off during normal operation.