SLVSB98A March   2012  – July 2015 TPS2379

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CDB Converter Disable Bar Pin Interface
      2. 8.3.2 CLS Classification
      3. 8.3.3 DEN Detection and Enable
      4. 8.3.4 GATE Auxiliary Gate Driver
        1. 8.3.4.1 External Boost Circuit (Q1, Q2, and RBLST) Considerations
      5. 8.3.5 Internal Pass MOSFET
      6. 8.3.6 T2P Type-2 PSE Indicator
      7. 8.3.7 VDD Supply Voltage
      8. 8.3.8 VSS
      9. 8.3.9 PowerPAD
    4. 8.4 Device Functional Modes
      1. 8.4.1 PoE Overview
        1. 8.4.1.1  Threshold Voltages
        2. 8.4.1.2  PoE Start-Up Sequence
        3. 8.4.1.3  Detection
        4. 8.4.1.4  Hardware Classification
        5. 8.4.1.5  Inrush and Start-up
        6. 8.4.1.6  Maintain Power Signature
        7. 8.4.1.7  Start-up and Operation
        8. 8.4.1.8  PD Hotswap Operation
        9. 8.4.1.9  CDB and T2P
        10. 8.4.1.10 Auxiliary Pass MOSFET Control
        11. 8.4.1.11 Using DEN to Disable PoE
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1 Input Bridges and Schottky Diodes
        2. 9.2.2.2 Protection, D1
        3. 9.2.2.3 Capacitor, C1
        4. 9.2.2.4 Detection Resistor, RDEN
        5. 9.2.2.5 Classification Resistor, RCLS
        6. 9.2.2.6 External Boost Circuit
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 EMI Containment
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations and OTSD
    4. 11.4 ESD
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The layout of the PoE front end should follow power and EMI/ESD best practice guidelines. A basic set of recommendations include:

  • Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diode bridges, TVS and 0.1-μF capacitor, and TPS2379.
  • All leads should be as short as possible with wide power traces and paired signal and return.
  • There should not be any crossovers of signals from one part of the flow to another.
  • Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage rails and between the input and an isolated converter output.
  • The TPS2379 should be located over split, local ground planes referenced to VSS for the PoE input and to RTN for the switched output.
  • Large copper fills and traces should be used on SMT power-dissipating devices, and wide traces or overlay copper fills should be used in the power path.

11.1.1 EMI Containment

  • Use compact loops for dv/dt and di/dt circuit paths (power loops and gate drives)
  • Use minimal, yet thermally adequate, copper areas for heat sinking of components tied to switching nodes (minimize exposed radiating surface).
  • Use copper ground planes (possible stitching) and top layer copper floods (surround circuitry with ground floods)
  • Use 4 layer PCB if economically feasible (for better grounding)
  • Minimize the amount of copper area associated with input traces (to minimize radiated pickup)
  • Use Bob Smith terminations, Bob Smith EFT capacitor, and Bob Smith plane
  • Use Bob Smith plane as ground shield on input side of PCB (creating a phantom or literal earth ground)
  • Use of ferrite beads on input (allow for possible use of beads or 0 ohm resistors)
  • Maintain physical separation between input-related circuitry and power circuitry (use ferrite beads as boundary line)
  • Possible use of common-mode inductors
  • Possible use of integrated RJ-45 jacks (shielded with internal transformer and Bob Smith terminations)
  • End-product enclosure considerations (shielding)

11.2 Layout Example

Figure 29 and Figure 30 show the top and bottom layer and assemblies of the TPS2378EVM-106 as a reference for optimum parts placement. A detailed PCB layout can be found in the user’s guide of the TPS2378EVM-106.

TPS2379 Layout_TOP.pngFigure 29. Recommended Layout Top View
TPS2379 Layout_BOT.pngFigure 30. Recommended Layout Bottom View

11.3 Thermal Considerations and OTSD

Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations assume that the TPS2379 device is the only heat source contributing to the PCB temperature rise. It is possible for a normally operating TPS2379 device to experience an OTSD event if it is excessively heated by a nearby device.

11.4 ESD

ESD requirements for a unit that incorporates the TPS2379 device have a much broader scope and operational implications than are used in TI’s testing. Unit-level requirements should not be confused with reference design testing that only validates the ruggedness of the TPS2379 device.