SLVSB98A March   2012  – July 2015 TPS2379

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CDB Converter Disable Bar Pin Interface
      2. 8.3.2 CLS Classification
      3. 8.3.3 DEN Detection and Enable
      4. 8.3.4 GATE Auxiliary Gate Driver
        1. 8.3.4.1 External Boost Circuit (Q1, Q2, and RBLST) Considerations
      5. 8.3.5 Internal Pass MOSFET
      6. 8.3.6 T2P Type-2 PSE Indicator
      7. 8.3.7 VDD Supply Voltage
      8. 8.3.8 VSS
      9. 8.3.9 PowerPAD
    4. 8.4 Device Functional Modes
      1. 8.4.1 PoE Overview
        1. 8.4.1.1  Threshold Voltages
        2. 8.4.1.2  PoE Start-Up Sequence
        3. 8.4.1.3  Detection
        4. 8.4.1.4  Hardware Classification
        5. 8.4.1.5  Inrush and Start-up
        6. 8.4.1.6  Maintain Power Signature
        7. 8.4.1.7  Start-up and Operation
        8. 8.4.1.8  PD Hotswap Operation
        9. 8.4.1.9  CDB and T2P
        10. 8.4.1.10 Auxiliary Pass MOSFET Control
        11. 8.4.1.11 Using DEN to Disable PoE
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1 Input Bridges and Schottky Diodes
        2. 9.2.2.2 Protection, D1
        3. 9.2.2.3 Capacitor, C1
        4. 9.2.2.4 Detection Resistor, RDEN
        5. 9.2.2.5 Classification Resistor, RCLS
        6. 9.2.2.6 External Boost Circuit
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 EMI Containment
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations and OTSD
    4. 11.4 ESD
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DDA Package
8-Pin HSOP
Top View
TPS2379 po_lvsb98.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
VDD 1 I Connect to positive PoE input power rail. Bypass with 0.1 µF to VSS.
DEN 2 I/O Connect 24.9 kΩ to VDD for detection. Pull to VSS disable pass MOSFET.
CLS 3 O Connect resistor from CLS to VSS to program classification current.
VSS 4 — Connect to negative power rail derived from PoE source.
RTN 5 O Drain of PoE pass MOSFET.
CDB 6 O Opendrain converter disable output, active low, referenced to RTN.
T2P 7 O Active low indicates type 2 PSE connected.
GATE 8 O Auxiliary gate driver output.
PowerPAD — — The PowerPAD must be connected to VSS. A large fill area is required to assist in heat dissipation.