SLUS634F November   2004  – January 2022 TPS2384

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 PMM Faults
      2. 8.3.2 Watchdog Timer
    4. 8.4 Device Functional Modes
      1. 8.4.1  Auto Mode
      2. 8.4.2  Auto Mode Functional Description
        1. 8.4.2.1 AM Discovery
        2. 8.4.2.2 AM Classification
        3. 8.4.2.3 AM Power Delivery
      3. 8.4.3  AM Faults and INTB Output
      4. 8.4.4  Over and Undervoltage Fault
      5. 8.4.5  Over Current or Current Limit Faults
      6. 8.4.6  Undercurrent Fault (DC Modulated Disconnect)
      7. 8.4.7  Power Management Mode (PMM)
        1. 8.4.7.1 13 PMM Functions
      8. 8.4.8  PMM Discovery 1
      9. 8.4.9  PMM Discovery 2
      10. 8.4.10 PMM Classification
      11. 8.4.11 PMM Legacy
      12. 8.4.12 PMM Rup Pwr
      13. 8.4.13 PMM RDWN
    5. 8.5 Programming
      1. 8.5.1 I2C Interface Description
      2. 8.5.2 Start and Stop
      3. 8.5.3 Chip Address
      4. 8.5.4 Chip Addressing
      5. 8.5.5 Data Write Cycle
      6. 8.5.6 Port and Register Cycle
      7. 8.5.7 Data Read Cycle
    6. 8.6 Register Maps
      1. 8.6.1 Register/Port Addressing Map
      2. 8.6.2 Common Read, Register Select
      3. 8.6.3 Common Write, Register Select = 1111 (Test Register)
      4. 8.6.4 Common Control Write, Register Select = 0001
      5. 8.6.5 Port Control Write 1, Register Select = 0010 (One Per Port)
      6. 8.6.6 Port Control Write 2, Register Select = 0011 (One Per Port)
      7. 8.6.7 Port Status Read 1, Register Select = 0100 (One Per Port)
      8. 8.6.8 Port Status Read 2, Register Select = 0101 (One Per Port)
      9. 8.6.9 A/D Results Registers (Discovery Current, Voltage, Current and Temperature)
        1. 8.6.9.1 Discovery Current — Lower Bits, Register Select = 0110 (One Per Port)
        2. 8.6.9.2 Discovery Current — Upper Bits, Register Select = 0111 (One Per Port)
        3. 8.6.9.3 Voltage — Lower Bits, Register Select = 1000 (One Per Port)
        4. 8.6.9.4 Voltage — Upper Bits, Register Select = 1001 (One Per Port)
        5. 8.6.9.5 Current — Lower Bits, Register Select = 1010 (One Per Port)
        6. 8.6.9.6 Current — Upper Bits, Register Select = 1011 (One Per Port)
        7. 8.6.9.7 Temperature — Lower Bits, Register Select = 1100 (One Per Port)
        8. 8.6.9.8 Temperature — Upper Bits, Register Select = 1101 (One Per Port)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 AC Disconnect Drive Circuit Detail
      2. 9.1.2 Connection of Unused Ports and Pins
      3. 9.1.3 Opto-isolator Interface
      4. 9.1.4 Port Protection from Electrical Transients
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Pin Bypass Capacitors
        2. 9.2.2.2 Per Port Components
        3. 9.2.2.3 Bias and Timing
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Local Circuits
      2. 11.1.2 System Protection Circuits
    2. 11.2 Layout Example
    3. 11.3 Thermal Consideration
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.5 Data Write Cycle

For a data write sequence, after the Port/Register address cycle, the TPS2384 accepts the eight bits of data as defined in the tables below. The data is latched into the previously selectedWrite Register, and the TPS2384 generates a data acknowledge pulse by pulling the SDA_O line low for one clock cycle. Common register functions act on all ports simultaneously. Per port registers are specific to the target port only.

To reset the interface, the host or controller subsequently generates a stop bit by releasing the SDA_I line during the clock-high portion of an SCL pulse.