SLUS634F November 2004 – January 2022 TPS2384
PRODUCTION DATA
For a data read sequence, after the register acknowledge bit, the controller device generates a stop condition. This action is followed by a second start condition, and retransmitting the device address as described in chip address above. For this cycle, however, the R/W bit is set to a 1 to signal the read operation. The TPS2384 again responds with an acknowledge pulse. The address acknowledge is then followed by sequentially presenting each of the eight data bits on the SDA_O line (MSB first), to be read by the host device on the rising edges of SCL. After eight bits are transmitted, the host acknowledges by pulling the SDA_I line high for one clock pulse. The completed data transfer is terminated with the host generating a stop condition.