5 Pin Configuration and Functions

NIC = No internal connection. Pins are floating.

NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection from unused pins.

NIC pins next to CINT pins must be tied to ground to prevent noise injection into A/D converter.

Figure 5-1 PAP Package64-Pin HTQFPTop View

NIC = No internal connection. Pins are floating.

NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection from unused pins.

NIC pins next to CINT pins must be tied to ground to prevent noise injection into A/D converter.

Figure 5-2 PJD Package64-Pin HTQFPTop View

Table 5-1 Pin Functions

PIN			I/O	DESCRIPTION
NAME	NO.
NAME	PAP	PDJ
Power and Ground
V48	60	5	I	48-V input to the device. This supply can have a range of 44 to 57 V. This pin must be decoupled with a 0.1-μF capacitor from V48 to AG1 placed as close to the device as possible.
V10	58	7	O	10-V analog supply. The 10-V reference is generated internally and connects to the main internal analog power bus. A 0.1-μF de-coupling capacitor must terminate as close to this node and the AG1 pin as possible. Do not use for an external supply.
V6.3	59	6	O	6.3-V analog supply. A 0.1-μF de-coupling capacitor must terminate as close to this pin and the AG1 pin as possible. Do not use for an external supply.
V3.3	24	41	O	3.3-V logic supply. The 3.3-V supply is generated internally and connects to the internal logic power bus. A 0.1-μF de-coupling capacitor must terminate as close to this node and the DG pin as possible. This output can be used as a low current supply to external logic.
V2.5	54	11	O	2.5-V reference supply. The V2.5 is generated internally and connects to the internal reference power bus. This pin must not be tied to any external supplies. A 0.1-μF de-coupling capacitor must terminate as close to this node and the RG pin as possible. Do not use for an external supply.
AG1	57	8	GND	Analog ground 1. This is the analog ground of the V6.3, V10 and V48 power systems. This pin must be externally tied to the common copper 48-V return plane. This pin must carry the low side of three de-coupling capacitors tied to V48, V10 and V6.3.
AG2	61	4	GND	Analog ground 2. This pin is the analog ground which ties to the substrate and ESD structures of the device. this pin must be externally tied to the common copper 48-V return plane. AG1 and AG2 must be tied together directly for the best noise immunity.
DG	23	42	GND	Digital ground. This pin connects to the internal logic ground bus. this pin must be externally tied to the common copper 48-V return plane.
RG	56	9	GND	Reference ground. This pin is a precision sense of the external ground plane. The integration capacitor (CINT) and the biasing resistor (RBIAS pin) must be tied to this ground. This ground must also be used to form a printed wiring board ground guard ring around the active node of the integration capacitor (CINT). It must tie to common copper 48-V return plane.
Port Analog Signal
P1	7	58	I	Port Positive. 48-V load sense pin. Terminal voltage is monitored and controlled differentially with respect to each Port N pin. Optionally, if the application warrants, this high-side path can be protected with the use of a self-resetting poly fuse.
P2	10	55	I
P3	39	26	I
P4	42	23	I
N1	6	59	I	Port negative. 48-V load return pin. The low side of the load is switched and protected by internal circuitry that limits the current.
N2	11	54	I
N3	38	27	I
N4	43	22	I
RET1	5	60	I	48-V return pin
RET2	12	53	I
RET3	37	28	I
RET4	44	21	I
CINT1	4	61	I	Integration capacitor This capacitor is used for the ramp A/D converter signal integration. Connect A 0.027- μF capacitor from this pin to RG. To minimize errors use a polycarbonate, poly-polypropylene, polystyrene or teflon capacitor type to prevent leakage. Other types of capacitors can be used with increased conversion error.
CINT2	13	52	I
CINT3	36	29	I
CINT4	45	20	I
Analog Signals
CT	53	12	I	This is a dual-purpose pin. When tied to an external capacitor this pin sets the internal clock. When the CT pin is grounded the SYN pin turns from a output to an input (see SYN pin description).
CT	53	12	I	The timing capacitor and the resistor on the RBIAS pin sets the internal clock frequency of the device. This internal clock is used for the internal state machine, integrating A/D counters, POR time out, faults and delay timers of each port. Using a 220-pF capacitor for CT and a 124-kΩ resistor for RBIAS sets the internal clock to 245 kHz and ensure IEEE 802.3af compliance along with maximizing the rejection of 60-Hz line frequency noise from A/D measurements.
RBIAS	55	10	I	Bias set resistor. This resistor sets all precision bias currents within the chip. This pin regulates to 1.25 V (V2.5/2) when a resistor is connected between RBIAS and RG. This voltage and RBIAS generate a current which is replicated and used throughout the chip. This resistor also works in conjunction with the capacitors on CT and CINT to set internal timing values. The RBIAS resistor must be connected RG. RBIAS is a high impedance input and care must be taken to avoid signal injection from the SYN pin or I²C signals.
SYN	52	13	I/O	This is a dual purpose pin. When the CT pin is connected to a timing capacitor this output pin is a 0-V to 3.3-V pulse of the internal clock which can be used to drive other TPS2384 SYN pins for elimination of a timing capacitor. When the CT pin is grounded this pin becomes an input pin that can be driven from a controller TPS2384 or any other clock generator signal.
AC_LO	51	14	O	Totem-pole output pin for AC Disconnect excitation.
AC_HI	50	15	O	Totem-pole output pin for AC Disconnect excitation.
Digital Signals
SCL	25	40	I	Serial clock input pin for the I²C interface.
SDA_I	26	39	I	Serial data input pin for the I²C interface. When tied to the SDA_O pin, this connection becomes the standard bi-directional serial data line (SDA)
SDA_O	27	38	O	Serial data open drain output for the I²C interface. When tied to the SDA_I pin, this connection becomes the standard bi-directional serial data line (SDA). This pin is an open drain output that can directly drive opto-coupler.
WD_DIS	22	43	I	The WD_DIS pin disables the watchdog timer function when connected to 3.3 V. The pin has internal 50-kΩ resistor to digital ground. The watchdog timer monitors the I²C clock pin (SCL) and the internal oscillator activity in power management mode and only the internal oscillator activity in auto mode.
INTB	20	45	O	This pin is an open-drain output that goes low if a fault condition occurs on any of the 4 ports.
ALTA/B	21	44	I	When this input is set to logic low there is no back-off time after a discovery failure. When this pin set to a logic high there is a back-off time (approximately 2 seconds) before initiating another discovery cycle. This pin has an internal 50-kΩ resistor pulldown to digital ground.
A1	28	37	I	Address 1 through 5. These pins are the I²C address select inputs. Select the appropriate binary address on these pins by connecting to digital ground for a logic low or tying to the V3.3 pin for a logic high. Each address line has an internal current source pulldown to digital ground.
A2	29	36	I
A3	30	35	I
A4	31	34	I
A5	32	33	I
MS	63	2	I	The MS pin selects either the auto mode (MS low) or the power management mode, PMM, (MS high). This pin can be held low for controller-less standalone applications. When MS is low and the POR timing cycle is complete the chip sequentially Discovers, Classifies and Powers on each port. When MS is set high the ports are controlled by register setting via the I²C bus. The MS pin has an internal 50-kΩ resistor pulldown to analog ground.
PORB	62	3	I	This pin can be used to override the internal POR. When held low, the I²C interface, all the state machines, and registers are held in reset. When all internal and external supplies are within specification, and this pin is set to a logic high level, the POR delay begins. The I²C interface and registers become active within 70 μs of this event and communications to read or preset registers can begin. The reset delay for the remainder of the chip then extinguishes in 1 second. This pin has an internal 50-kΩ resistor pulldown to analog ground.