SLUSBX9I March   2014  – July 2019 TPS23861

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Detailed Pin Description
      2. 7.1.2 I2C Detailed Pin Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Detection Resistance Measurement
      2. 7.3.2  Physical Layer Classification
      3. 7.3.3  Class and Detect Fields
      4. 7.3.4  Register State Following a Fault
      5. 7.3.5  Disconnect
      6. 7.3.6  Disconnect Threshold
      7. 7.3.7  Fast Shutdown Mode
      8. 7.3.8  Legacy Device Detection
      9. 7.3.9  VPWR Undervoltage and UVLO Events
      10. 7.3.10 Timer-Deferrable Interrupt Support
      11. 7.3.11 A/D Converter and I2C Interface
      12. 7.3.12 Independent Operation when the AUTO Bit is Set
      13. 7.3.13 I2C Slave Address and AUTO Bit Programming
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off
      2. 7.4.2 Manual
      3. 7.4.3 Semi-Auto
      4. 7.4.4 Auto
      5. 7.4.5 Push-Button Power On Response
      6. 7.4.6 TSTART Indicators of Detect and Class Failures
      7. 7.4.7 Device Power On Initialization
    5. 7.5 Register Map – I2C-Addressable
      1. 7.5.1  Interrupt Register
      2. 7.5.2  Interrupt Enable Register
      3. 7.5.3  Power Event Register
      4. 7.5.4  Detection Event Register
      5. 7.5.5  Fault Event Register
      6. 7.5.6  Start/ILIM Event Register
      7. 7.5.7  Supply Event Register
      8. 7.5.8  Port n Status Register
        1. 7.5.8.1 Port 1 Status Register
        2. 7.5.8.2 Port 2 Status Register
        3. 7.5.8.3 Port 3 Status Register
        4. 7.5.8.4 Port 4 Status Register
      9. 7.5.9  Power Status Register
      10. 7.5.10 I2C Slave Address Register
      11. 7.5.11 Operating Mode Register
      12. 7.5.12 Disconnect Enable Register
      13. 7.5.13 Detect/Class Enable Register
      14. 7.5.14 Port Power Priority Register
      15. 7.5.15 Timing Configuration Register
      16. 7.5.16 General Mask 1 Register
      17. 7.5.17 Detect/Class Restart Register
      18. 7.5.18 Power Enable Register
      19. 7.5.19 Reset Register
      20. 7.5.20 Legacy Detect Mode Register
      21. 7.5.21 Two-Event Classification Register
      22. 7.5.22 Interrupt Timer Register
      23. 7.5.23 Disconnect Threshold Register
        1. 7.5.23.1 Bits Description
      24. 7.5.24 ICUTnm CONFIG Register
        1. 7.5.24.1 ICUT21 CONFIG Register
        2. 7.5.24.2 ICUT43 CONFIG Register
        3. 7.5.24.3 Bits Description
      25. 7.5.25 Temperature Register
      26. 7.5.26 Input Voltage Register
      27. 7.5.27 Port n Current Register
        1. 7.5.27.1 Port 1 Current Register
        2. 7.5.27.2 Port 2 Current Register
        3. 7.5.27.3 Port 3 Current Register
        4. 7.5.27.4 Port 4 Current Register
      28. 7.5.28 Port n Voltage Register
        1. 7.5.28.1 Port 1 Voltage Register
        2. 7.5.28.2 Port 2 Voltage Register
        3. 7.5.28.3 Port 3 Voltage Register
        4. 7.5.28.4 Port 4 Voltage Register
      29. 7.5.29 PoE Plus Register
      30. 7.5.30 Firmware Revision Register
      31. 7.5.31 I2C Watchdog Register
      32. 7.5.32 Device ID Register
      33. 7.5.33 Cool Down/Gate Drive Register
      34. 7.5.34 Port n Detect Resistance Register
        1. 7.5.34.1 Port 1 Detect Resistance Register
          1. 7.5.34.1.1 Port 2 Detect Resistance Register
          2. 7.5.34.1.2 Port 3 Detect Resistance Register
          3. 7.5.34.1.3 Port 4 Detect Resistance Register
      35. 7.5.35 Port n Detect Voltage Difference Register
        1. 7.5.35.1 Port 1 Detect Voltage Difference Register
        2. 7.5.35.2 Port 2 Detect Voltage Difference Register
        3. 7.5.35.3 Port 3 Detect Voltage Difference Register
        4. 7.5.35.4 Port 4 Detect Voltage Difference Register
      36. 7.5.36 Reserved Registers
  8. 8 Application and Implementation
    1. 8.1 Introduction to PoE
    2. 8.2 Application Information
      1. 8.2.1 Kelvin Current Sensing Resistor
      2. 8.2.2 Connections on Unused Ports
    3. 8.3 Typical Application
      1. 8.3.1 Two Port, Auto Mode Application with External Port Reset
        1. 8.3.1.1 Design Requirements
      2. 8.3.2 Four Port, Auto Mode Application
        1. 8.3.2.1 Design Requirements
      3. 8.3.3 Eight Port, Semi-Auto Mode Application Using MSP430 Micro-Controller
        1. 8.3.3.1 Design Requirements
      4. 8.3.4 Detailed Design Procedure
        1. 8.3.4.1 Power Pin Bypass Capacitors
        2. 8.3.4.2 Per Port Components
        3. 8.3.4.3 System Level Components (not shown in the schematic diagrams)
      5. 8.3.5 Application Curves
    4. 8.4 System Examples
      1. 8.4.1 Overcurrent and Overload Protection
      2. 8.4.2 Inrush Protection
      3. 8.4.3 ICUT Current Limit
      4. 8.4.4 Foldback Protection (ILIM)
      5. 8.4.5 Kelvin Current Sensing Resistor
  9. 9 Power Supply Recommendations
    1. 9.1 VDD
    2. 9.2 VPWR
    3. 9.3 VPWR-RESET Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Port Current Kelvin Sensing
    2. 10.2 Layout Example
      1. 10.2.1 Component Placement and Routing Guidelines
        1. 10.2.1.1 Power Pin Bypass Capacitors
        2. 10.2.1.2 Per-Port Components
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.8 Legacy Device Detection

Legacy PDs which are not compliant with IEEE 802.3at can be identified on port n under control of the LEGMOD field in the Legacy Detect Mode Register. Two modes of legacy detection are supported. When LEGMODn = 10, port n is probed for IEEE 802.3at-based compliance (based on resistance measurement) followed by a capacitance-based detection scheme for legacy devices. When LEGMODn= 01, port n performs a capacitance-based detection scheme only. This allows the host to probe for a potential legacy PD without pre-charging the PD capacitance before trying to measure the value of the capacitance.

To measure capacitance, a fixed charge is injected into the Power Interface (PI) and the voltage difference induced by the charge is measured and reported in the Port n Detect Voltage Difference Registers. The capacitance is inversely proportional to the voltage difference. The voltage difference is compared against thresholds to accept capacitance values above 6 µF pursuant to the qualifications which follow.

The Port n Detect Voltage Difference Register consists of two contiguous bytes in the I2C addressable register space. Together these registers contain a 12-bit unsigned representation of the voltage difference along with a 4-bit status field named VDSn. When VDSn = 0001 the voltage-difference value represents a valid measurement. The capacitance measurement may fail due to an excessively small or large capacitance, or an input capacitance which cannot be discharged because it is behind a diode. These cases are reported in the VDSn field as well as in the DETECT Pn field in the Port n Status Registers. See Table 5.

Table 5. Capacitance Measurement Characteristics and Capabilities

PARAMETER CONDITIONS VALUE UNIT
Minimum measurable capacitance Maximum 500-kΩ parallel resistance; maximum measurement voltage of 16.5 V at port 6.1 μF
Maximum measurable capacitance Minimum 17-kΩ parallel resistance 100 μF
Maximum measurable capacitance Minimum 10-kΩ parallel resistance 67 μF
Nominal port charging current 540 μA
Nominal measurement time 150 ms
Minimum voltage at port for commencement of measurement 0.4 V
Maximum voltage at port for commencement of measurement 2.4 V
Duration of port-discharge period First discharge attempt 250 ms
Duration of port-discharge period Second discharge attempt 500 ms
Maximum voltage at port at the beginning or end of measurement 16.5 V

A resistance in parallel with the capacitance at the input of the PD affects the accuracy of the capacitance-measurement algorithm. A parallel resistance causes the capacitance on the port to appear higher. This fact is reflected in Table 5 . Capacitance up to 100 μF can be measured with a parallel resistance as low as 17 kΩ, whereas if the parallel resistance is as low as 10-kΩ, capacitance up to 67 μF can be measured.

The voltage on the port must be in the range of 0.4 V to 2.4 V to begin capacitance measurement. This voltage as measured at the PSE includes the voltage drops across any diodes in the path of the capacitance. If the voltage measured is too high (due to charge on the PD capacitance), the TPS23861 makes two attempts to discharge the port by applying a 100-kΩ load across the port. The first discharge attempt is 250-ms duration; the second attempt 500 ms.

NOTE

It may not be possible to discharge the PD capacitance rapidly if the capacitance is on the other side of a diode.

If the capacitance-measurement algorithm is unable to discharge the port to less than 2.4 V after two attempts, the algorithm terminates the attempt to measure port capacitance, and report an Unable to achieve 2.4 V to take first measurement status in the VDSn field of the Port n Detect Voltage Difference Registers. A status of Capacitance measurement invalid: Insufficient Δv measured is reported in the Port n Status Registers. A status of Unable to discharge PD input capacitance to 2.4 V before timeout, is reported in the VDSn field of the Port n Detect Voltage Difference Registers. The host has the option of imposing a longer discharge time and retrying.

Erratic results may be obtained when performing legacy detect in Semi-Auto Mode due to the repeated charging of the load. If the capacitive load is behind a diode or is in parallel with a high resistance, the capacitor may eventually charge beyond 2.4 V, and the capacitance measurement fails. Manual Mode is recommended for legacy detect when there is no information about the load, or if the load input capacitance charges beyond 2.4 V in Semi-Auto Mode.

If the port is open or a small capacitance is present on the port, the port voltage rises quickly when the capacitance-measuring current is applied. The voltage on the port is limited to approximately 18 V by an internal clamp. A status of Capacitance measurement invalid: Detect measurement beyond clamp voltage is reported in the DETECT Pn field of the Port n Status Registers. Depending on the size of the small capacitance, a status of First measurement exceeds VDet-clamp (min) or Second measurement exceeds VDet-clamp (min) is reported in the VDSn field of the PORT n Detect Voltage Difference Registers.

If a large capacitance or short circuit is present on the port, the port voltage will not change sufficiently over the port charging time to assure a reliable measurement. In this case, a status of Capacitance measurement invalid: Insufficient Δv measured is reported in the Port n Status Registers, and a status of Δv < 0.5 V (insufficient signal) or Unable to achieve 0.4V to take first measurement before timeout is reported in the VDSn field of the Port n Detect Voltage Difference Registers.

Legacy detect is an exceptional condition which warrants special handling by the host system. Consequently, legacy-detect operation will not be fully supported in Auto Mode. If a legacy device is detected during detection in any mode of operation, the detect status is reported as Legacy Detect in the Port n Status Register Detect Pn field. It is up to the host to power on the port. If a port is in Auto Mode, legacy detection is enabled and a legacy device is detected, the detect status is reported as Legacy Detect in the Port n Status Registers Detect Pn field, but the port will not power on automatically. In this respect, operation of the port is identical to the Semi-Auto Mode.

In general, it is expected that a legacy device will not respond to a request for classification. Therefore, if the portis in Semi-Auto, Auto Mode or Manual Mode and LEGMOD = 01, the PSE will not automatically initiate a classification cycle even if the CLEn bit is set. On the other hand, if LEGMOD = 10, the TPS23861 is operating in Semi-Auto or Auto Mode, classification is enabled via the CLEn bit, and a Resistance valid detect status is returned in response to a standard resistance detection cycle, the TPS23861 follows the standard resistance detection cycle with a classification cycle. Furthermore, following classification, if in Auto Mode, if the classification status is not unknown, class mismatch or overcurrent, the port automatically powers up. Additionally if LEGMOD = 10, it is possible to initiate a classification cycle under manual control using the CLEn bit in the Detect/Class Enable Register or the RCLn bit in the Detect/Class Restart Register or power on the port under manual control using the PWONn bit in the Power Enable Register.

If LEGMODn = 10, and a Resistance valid detect status is returned in response to a standard resistance detection cycle the TPS23861 will not attempt to measure capacitance on the PI.