SLUSC25A February 2015 – August 2017 TPS2388
PRODUCTION DATA.
Cmd Code | Register or Command Name | I2C R/W | Data Byte | RST State | Bits Description | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
INTERRUPTS | ||||||||||||
00h | INTERRUPT | RO | 1 | 1000,0000b(1) | SUPF | STRTF | IFAULT | CLASC | DETC | DISF | PGC | PEC |
01h | INTERRUPT MASK | R/W | 1 | 1000,0000b | SUMSK | STMSK | IFMSK | CLMSK | DEMSK | DIMSK | PGMSK | PEMSK |
EVENT | ||||||||||||
02h | POWER EVENT | RO | 1 | 0000,0000b | Power Good status change | Power Enable status change | ||||||
03h | CoR | 1 | PGC4 | PGC3 | PGC2 | PGC1 | PEC4 | PEC3 | PEC2 | PEC1 | ||
04h | DETECTION EVENT | RO | 1 | 0000,0000b | Classification | Detection | ||||||
05h | CoR | 1 | CLSC4 | CLSC3 | CLSC2 | CLSC1 | DETC4 | DETC3 | DETC2 | DETC1 | ||
06h | FAULT EVENT | RO | 1 | 0000,0000b | Disconnect occurred | ICUT fault occurred | ||||||
07h | CoR | 1 | DISF4 | DISF3 | DISF2 | DISF1 | ICUT4 | ICUT3 | ICUT2 | ICUT1 | ||
08h | START/ILIM EVENT | RO | 1 | 0000,0000b | ILIM fault occurred | START fault occurred | ||||||
09h | CoR | 1 | ILIM4 | ILIM3 | ILIM2 | ILIM1 | STRT4 | STRT3 | STRT2 | STRT1 | ||
0Ah | SUPPLY EVENT | RO | 1 | 0111,0000b(2) | TSD | VDUV | VDWRN | VPUV | Rsvd | Rsvd | Rsvd | Rsvd |
0Bh | CoR | 1 | ||||||||||
STATUS | ||||||||||||
0Ch | PORT 1 STATUS | RO | 1 | 0000,0000b | Rsvd | CLASS Port 1 | DETECT Port 1 | |||||
0Dh | PORT 2 STATUS | RO | 1 | 0000,0000b | Rsvd | CLASS Port 2 | DETECT Port 2 | |||||
0Eh | PORT 3 STATUS | RO | 1 | 0000,0000b | Rsvd | CLASS Port 3 | DETECT Port 3 | |||||
0Fh | PORT 4 STATUS | RO | 1 | 0000,0000b | Rsvd | CLASS Port 4 | DETECT Port 4 | |||||
10h | POWER STATUS | RO | 1 | 0000,0000b | PG4 | PG3 | PG2 | PG1 | PE4 | PE3 | PE2 | PE1 |
11h | PIN STATUS | RO | 1 | 0,A[4:0],0,0 | Rsvd | SLA4 | SLA3 | SLA2 | SLA1 | SLA0 | Rsvd | Rsvd |
CONFIGURATION | ||||||||||||
12h | OPERATING MODE | R/W | 1 | 0000,0000b | Port 4 Mode | Port 3 Mode | Port 2 Mode | Port 1 Mode | ||||
13h | DISCONNECT ENABLE | R/W | 1 | 0000,0000b | Rsvd | Rsvd | Rsvd | Rsvd | DCDE4 | DCDE3 | DCDE2 | DCDE1 |
14h | DETECT/CLASS ENABLE | R/W | 1 | 0000,0000b | CLE4 | CLE3 | CLE2 | CLE1 | DETE4 | DETE3 | DETE2 | DETE1 |
15h | PWRPR/ICUT DISABLE | R/W | 1 | 0000,0000b | OSS4 | OSS3 | OSS2 | OSS1 | DCUT4 | DCUT3 | DCUT2 | DCUT1 |
16h | TIMING CONFIG | R/W | 1 | 0000,0000b | TLIM | TSTART | TOVLD | TMPDO | ||||
17h | GENERAL MASK | R/W | 1 | 1000,0000b | INTEN | Rsvd | nbitACC | MbitPrty | CLCHE | DECHE | Rsvd | |
PUSH BUTTONS | ||||||||||||
18h | DETECT/CLASS Restart | WO | 1 | 0000,0000b | RCL4 | RCL3 | RCL2 | RCL1 | RDET4 | RDET3 | RDET2 | RDET1 |
19h | POWER ENABLE | WO | 1 | 0000,0000b | POFF4 | POFF3 | POFF2 | POFF1 | PWON4 | PWON3 | PWON2 | PWON1 |
1Ah | RESET | WO | 1 | 0000,0000b | CLRAIN | CLINP | Rsvd | RESAL | RESP4 | RESP3 | RESP2 | RESP1 |
GENERAL/SPECIALIZED | ||||||||||||
1Bh | ID | RO | 1 | Mf[4:0],IC[2:0] | MFR ID | IC Version | ||||||
1Ch | Reserved | CoR | 1 | 0000,0000b | Reserved | Reserved | ||||||
1Eh | POLICE 21 CONFIG | R/W | 1 | 1111,1111b | POLICE Port 2 | POLICE Port 1 | ||||||
1Fh | POLICE 43 CONFIG | R/W | 1 | 1111,1111b | POLICE Port 4 | POLICE Port 3 | ||||||
23h | IEEE Power Enable | WO | 1 | 0000,0000b | T2PON4 | T2PON3 | T2PON2 | T2PON1 | T1PON4 | T1PON3 | T1PON2 | T1PON1 |
24h | Power-on FAULT | RO | 1 | 0000,0000b | PF Port 4 | PF Port 3 | PF Port 2 | PF Port 1 | ||||
25h | CoR | 1 | ||||||||||
26h | RE-MAPPING | R/W | 1 | 1110,0100b | Physical re-map Logical Port 4 | Physical re-map Logical Port 3 | Physical re-map Logical Port 2 | Physical re-map Logical Port 1 | ||||
27h | Multi-bit Power Priority 21 | R/W | 1 | 0000,0000b | Rsvd | Port 2 | Rsvd | Port 1 | ||||
28h | Multi-bit Power Priority 43 | R/W | 1 | 0000,0000b | Rsvd | Port 4 | Rsvd | Port 3 | ||||
29h-2Bh | Reserved | R/W | 1 | 0000,0000b | Rsvd | Rsvd | Rsvd | Rsvd | Rsvd | Rsvd | Rsvd | Rsvd |
2Ch | TEMPERATURE | RO | 1 | 0000,0000b | Temperature (bits 7 to 0) | |||||||
2Eh | INPUT VOLTAGE | RO | 2 | 0000,0000b | Input Voltage: LSByte | |||||||
2Fh | RO | 0000,0000b | Rsvd | Rsvd | Input Voltage: MSByte (bits 13 to 8) | |||||||
EXTENDED REGISTER SET – PORT PARAMETRIC MEASUREMENT | ||||||||||||
30h | PORT 1 CURRENT | RO | 2 | 0000,0000b | Port 1 Current: LSByte | |||||||
31h | RO | 0000,0000b | Rsvd | Rsvd | Port 1 Current: MSByte (bits 13 to 8) | |||||||
32h | PORT 1 VOLTAGE | RO | 2 | 0000,0000b | Port 1 Voltage: LSByte | |||||||
33h | RO | 0000,0000b | Rsvd | Rsvd | Port 1 Voltage: MSByte (bits 13 to 8) |
Cmd Code | Register or Command Name | I2C R/W | Data Byte | RST State | Bits Description | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
34h | PORT 2 CURRENT | RO | 2 | 0000,0000b | Port 2 Current: LSByte | |||||||
35h | RO | 0000,0000b | Rsvd | Rsvd | Port 2 Current: MSByte (bits 13 to 8) | |||||||
36h | PORT 2 VOLTAGE | RO | 2 | 0000,0000b | Port 2 Voltage: LSByte | |||||||
37h | RO | 0000,0000b | Rsvd | Rsvd | Port 2 Voltage: MSByte (bits 13 to 8) | |||||||
38h | PORT 3 CURRENT | RO | 2 | 0000,0000b | Port 3 current: LSByte | |||||||
39h | RO | 0000,0000b | Rsvd | Rsvd | Port 3 Current: MSByte (bits 13 to 8) | |||||||
3Ah | PORT 3 VOLTAGE | RO | 2 | 0000,0000b | Port 3 Voltage: LSByte | |||||||
3Bh | RO | 0000,0000b | Rsvd | Rsvd | Port 3 Voltage: MSByte (bits 13 to 8) | |||||||
3Ch | PORT 4 CURRENT | RO | 2 | 0000,0000b | Port 4 current: LSByte | |||||||
3Dh | RO | 0000,0000b | Rsvd | Rsvd | Port 4 Current: MSByte (bits 13 to 8) | |||||||
3Eh | PORT 4 VOLTAGE | RO | 2 | 0000,0000b | Port 4 Voltage: LSByte | |||||||
3Fh | RO | 0000,0000b | Rsvd | Rsvd | Port 4 Voltage: MSByte (bits 13 to 8) | |||||||
CONFIGURATION/OTHERS | ||||||||||||
40h | PoE PLUS | R/W | 1 | 0000,0000b | PoEP4 | PoEP3 | PoEP2 | PoEP1 | Rsvd | Rsvd | Rsvd | TPON |
41h | FIRMWARE REVISION | RO | 1 | RRRR,RRRRb | Firmware Revision | |||||||
42h | I2C WATCHDOG | R/W | 1 | 0001,0110b | Rsvd | Rsvd | Rsvd | Watchdog Disable | WDS | |||
43h | DEVICE ID | RO | 1 | 110,sr[4:0] | Device ID number | Silicon Revision number | ||||||
PORT SIGNATURE MEASUREMENTS | ||||||||||||
44h | P1 DETECT RESISTANCE | RO | 1 | 0000,0000b | Port 1 Resistance | |||||||
45h | P2 DETECT RESISTANCE | RO | 1 | 0000,0000b | Port 2 Resistance | |||||||
46h | P3 DETECT RESISTANCE | RO | 1 | 0000,0000b | Port 3 Resistance | |||||||
47h | P4 DETECT RESISTANCE | RO | 1 | 0000,0000b | Port 4 Resistance | |||||||
48h-6Fh | Reserved | R/W | 1 | 0000,0000b | Reserved |
Cmd Code | Register or Command Name | Bits Description | Configuration A | Configuration B |
---|---|---|---|---|
00h | INTERRUPT | INT bits P1-4, P5-8 | Separate mask and interrupt result per group of 4 ports. The Supply event bit is repeated twice. |
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01h | INTERRUPT MASK | MSK bits P1-4, P5-8 | ||
02h | POWER EVENT | PGC_PEC P4-1, P8-5 | Separate event byte per group of 4 ports. | |
03h | ||||
04h | DETECTION EVENT | CLS_DET P4-1, P8-5 | ||
05h | ||||
06h | FAULT EVENT | DIS_ICUT P4-1, P8-5 | ||
07h | ||||
08h | START/ILIM EVENT | ILIM_STR P4-1, P8-5 | ||
09h | ||||
0Ah | SUPPLY EVENT | TSD, VDUV, VDUW, VPUV | Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result. Clearing at least one VPUV/VDUV also clears the other one. |
|
0Bh | ||||
0Ch | PORT 1 STATUS | CLS&DET1_CLS&DET5 | Separate Status byte per port | |
0Dh | PORT 2 STATUS | CLS&DET2_CLS&DET6 | ||
0Eh | PORT 3 STATUS | CLS&DET3_CLS&DET7 | ||
0Fh | PORT 4 STATUS | CLS&DET4_CLS&DET8 | ||
10h | POWER STATUS | PG_PE P4-1, P8-5 | Separate status byte per group of 4 ports | |
11h | PIN STATUS | A4-A1,A0 | Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result, except that A0 = 0 (port 1 to 4) or 1 (port 5 to 8). | Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result, including A0 = 0. |
12h | OPERATING MODE | MODE P4-1, P8-5 | Separate Mode byte per group of 4 ports. | |
13h | DISCONNECT ENABLE | DCDE P4-1, P8-5 | Separate DC disconnect enable byte per group of 4 ports. | |
14h | DETECT/CLASS ENABLE | CLE_DETE P4-1, P8-5 | Separate Detect/Class Enable byte per group of 4 ports. | |
15h | PWRPR/ICUT DISABLE | OSS_DCUT P4-1, P8-5 | Separate OSS/DCUT byte per group of 4 ports. | |
16h | TIMING CONFIG | TLIM_TSTRT_TOVLD_TMPDO P4-1, P8-5 |
Separate Timing byte per group of 4 ports. | |
17h | GENERAL MASK | P4-1, P8-5 including n-bit access | Separate byte per group of 4 ports. n-bit access: Setting this in at least one of the virtual quad register space is enough to enter Config B mode. To go back to config A, clear both. MbitPrty: Setting this in at least one of the virtual quad register space is enough to enter 3-bit shutdown priority. To go back to 1-bit shutdown, clear both MbitPrty bits. |
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18h | DETECT/CLASS Restart | RCL_RDET P4-1, P8-5 | Separate DET/CL RST byte per group of 4 ports | |
19h | POWER ENABLE | POF_PWON P4-1, P8-5 | Separate POF/PWON byte per group of 4 ports | |
1Ah | RESET | P4-1, P8-5 | Separate byte per group of 4 ports, Clear Int pin and Clear All int. However, If at least one of the IC reset bits is set – the whole chip has a POR. |
Separate byte per group of 4 ports. However, if any of the following bit is set for one 4-port group, the corresponding action is applied to both 4-port groups: Reset IC, Clear Int pin, and Clear All Int. |
1Bh | ID | Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result unless modified through I2C. | ||
1Eh | POLICE 21 CONFIG | POL2&1, POL6&5 | Separate Policing byte per group of 2 ports. | |
1Fh | POLICE 43 CONFIG | POL4&3, POL8&7 | ||
23h | IEEE Power Enable | T2P_T1P P4-1, P8-5 | Separate IEEE Power Enable byte per group of 2 ports | |
24h | Power-on FAULT | PF P4-1, P8-5 | Separate Power-on FAULT byte per group of 4 ports | |
25h | ||||
26h | PORT REMAPPING | Logical P4-1, P8-5 | Separate Remapping byte per group of 4 ports. Reinitialized only if POR or RESET pin. Kept unchanged if 0x1A IC reset or CPU watchdog reset. |
|
2Ch | TEMPERATURE | TEMP P1-4, P5-8 | Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result. | |
2Eh | INPUT VOLTAGE | VPWR P1-4, P5-8 | Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result. | |
2Fh | ||||
30h | PORT 1 CURRENT | I1, I5 | Separate 2-byte per group of 4 ports | Separate 2-byte per group of 4 ports. 2-byte Read at 0x30 gives I1 4-byte Read at 0x30 gives I1, I5. |
31h | N/A | 2-byte Read at 0x31 gives I5. | ||
32h | PORT 1 VOLTAGE | V1, V5 | Separate 2-byte per group of 4 ports | 2-byte Read at 0x32 gives V1 4-byte Read at 0x32 gives V1, V5. |
33h | N/A | 2-byte Read at 0x33 gives V5. | ||
34h | PORT 2 CURRENT | I2, I6 | Separate 2-byte per group of 4 ports | 2-byte Read at 0x34 gives I2 4-byte Read at 0x34 gives I2, I6. |
35h | N/A | 2-byte Read at 0x35 gives I6. | ||
36h | PORT 2 VOLTAGE | V2, V6 | Separate 2-byte per group of 4 ports | 2-byte Read at 0x36 gives V2 4-byte Read at 0x36 gives V2, V6. |
37h | N/A | 2-byte Read at 0x37 gives V6. | ||
38h | PORT 3 CURRENT | I3, I7 | Separate 2-byte per group of 4 ports | 2-byte Read at 0x38 gives I3 4-byte Read at 0x38 gives I3, I7. |
39h | N/A | 2-byte Read at 0x39 gives I7. | ||
3Ah | PORT 3 VOLTAGE | V3, V7 | Separate 2-byte per group of 4 ports | 2-byte Read at 0x3A gives V3 4-byte Read at 0x3A gives V3, V7. |
3Bh | N/A | 2-byte Read at 0x3B gives V7. | ||
3Ch | PORT 4 CURRENT | I4, I8 | Separate 2-byte per group of 4 ports | 2-byte Read at 0x3C gives I4 4-byte Read at 0x3C gives I4, I8. |
3Dh | N/A | 2-byte Read at 0x3D gives I8. | ||
3Eh | PORT 4 VOLTAGE | V4, V8 | Separate 2-byte per group of 4 ports | 2-byte Read at 0x3E gives V4 4-byte Read at 0x3E gives V4, V8. |
3Fh | N/A | 2-byte Read at 0x3F gives V8. | ||
40h | PoE PLUS | PoEP_TPON, P4-1, P8-5 | TPON setting: separate setting per group of 4 ports. Separate PoEP config byte per group of 4 ports. |
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41h | FIRMWARE REVISION | FRV P1-4, P5-8 | Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result. | |
42h | I2C WATCHDOG | P1-4, P5-8 | IWD3-0: if at least one of the two 4-port settings is different than 1011b, the watchdog is enabled for all 8 ports. WDS: Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same WDS result. Each WDS bit needs to be cleared individually through I2C. |
|
43h | DEVICE ID | DID_SR P1-4, P5-8 | Both 8-bit registers (port 1 to 4 and port 5 to 8) must show the same result unless modified through I2C. | |
44h | PORT 1 RESISTANCE | RDET1, RDET5 | Separate byte per port. Detection resistance always updated, detection good or bad. |
|
45h | PORT 2 RESISTANCE | RDET2, RDET6 | ||
46h | PORT 3 RESISTANCE | RDET3, RDET7 | ||
47h | PORT 4 RESISTANCE | RDET4, RDET8 |