SLUSC25A February 2015 – August 2017 TPS2388
PRODUCTION DATA.
COMMAND = 04h with 1 Data Byte, Read only
COMMAND = 05h with 1 Data Byte, Clear on Read
Active high, each bit corresponds to a particular event that occurred.
Each bit xxx1-4 represents an individual port.
A read at each location (04h or 05h) returns the same register data with the exception that the Clear on Read command clears all bits of the register. These bits are cleared when port n is turned off.
If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.
Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLSC4 | CLSC3 | CLSC2 | CLSC1 | DETC4 | DETC3 | DETC2 | DETC1 |
R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
CR-0 | CR-0 | CR-0 | CR-0 | CR-0 | CR-0 | CR-0 | CR-0 |
LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7–4 | CLSC4–CLSC1 | R or CR | 0 | Indicates that at least one classification cycle occurred if the CLCHE bit in General Mask register is low. Conversely, it indicates when a change of class occurred if the CLCHE bit is set. 1 = At least one classification cycle occurred (if CLCHE = 0) or a change of class occurred (CLCHE = 1) 0 = No classification cycle occurred (if CLCHE = 0) or no change of class occurred (CLCHE = 1) |
3–0 | DETC4–DETC1 | R or CR | 0 | Indicates that at least one detection cycle occurred if the DECHE bit in General Mask register is low. Conversely, it indicates when a change in detection occurred if the DECHE bit is set. 1 = At least one detection cycle occurred (if DECHE = 0) or a change in detection occurred (DECHE = 1) 0 = No detection cycle occurred (if DECHE = 0) or no change in detection occurred (DECHE = 1) |