SLUSC25A February   2015  – August 2017 TPS2388

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2. 5.1 Detailed Pin Description
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Port Remapping
      2. 8.3.2 Port Power Priority
      3. 8.3.3 A/D Converter
      4. 8.3.4 I2C Watchdog
      5. 8.3.5 Foldback Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Port Operating Modes
        1. 8.4.1.1 Semiauto
        2. 8.4.1.2 Manual
        3. 8.4.1.3 Power Off
      2. 8.4.2 Detection
      3. 8.4.3 Classification
      4. 8.4.4 DC Disconnect
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1  Complete Register Set
      2. 8.6.2  INTERRUPT Register
        1. Table 4. INTERRUPT Register Field Descriptions
      3. 8.6.3  INTERRUPT MASK Register
        1. Table 5. INTERRUPT MASK Register Field Descriptions
      4. 8.6.4  POWER EVENT Register
        1. Table 6. POWER EVENT Register Field Descriptions
      5. 8.6.5  DETECTION EVENT Register
        1. Table 7. DETECTION EVENT Register Field Descriptions
      6. 8.6.6  FAULT EVENT Register
        1. Table 8. FAULT EVENT Register Field Descriptions
      7. 8.6.7  START/ILIM EVENT Register
        1. Table 9. START/ILIM EVENT Register Field Descriptions
      8. 8.6.8  SUPPLY EVENT Register
        1. Table 10. SUPPLY EVENT Register Field Descriptions
      9. 8.6.9  PORT 1 STATUS Register
      10. 8.6.10 PORT 2 STATUS Register
      11. 8.6.11 PORT 3 STATUS Register
      12. 8.6.12 PORT 4 STATUS Register
        1. Table 11. PORT STATUS Register Field Descriptions
      13. 8.6.13 POWER STATUS Register
        1. Table 12. POWER STATUS Register Field Descriptions
      14. 8.6.14 Pin Status Register
        1. Table 13. Pin Status Register Field Descriptions
      15. 8.6.15 OPERATING MODE Register
        1. Table 14. OPERATING MODE Register Field Descriptions
      16. 8.6.16 DISCONNECT ENABLE Register
        1. Table 15. DISCONNECT ENABLE Register Field Descriptions
      17. 8.6.17 DETECT/CLASS ENABLE Register
        1. Table 16. DETECT/CLASS ENABLE Register Field Descriptions
      18. 8.6.18 Port Power Priority/ICUT Disable Register Name
        1. Table 17. Port Power Priority/ICUT Disable Register Field Descriptions
      19. 8.6.19 TIMING CONFIGURATION Register
        1. Table 18. TIMING CONFIGURATION Register Field Descriptions
      20. 8.6.20 GENERAL MASK Register
        1. Table 19. GENERAL MASK Register Field Descriptions
      21. 8.6.21 DETECT/CLASS RESTART Register
        1. Table 20. DETECT/CLASS RESTART Register Field Descriptions
      22. 8.6.22 POWER ENABLE Register
        1. Table 21. POWER ENABLE Register Field Descriptions
      23. 8.6.23 RESET Register
        1. Table 22. RESET Register Field Descriptions
      24. 8.6.24 ID Register
        1. Table 23. ID Register Field Descriptions
      25. 8.6.25 Police 21 Configuration Register
      26. 8.6.26 Police 43 Configuration Register
        1. Table 24. Police 43 Register Field Descriptions
      27. 8.6.27 IEEE Power Enable Register
        1. Table 25. IEEE Power Enable Register Field Descriptions
      28. 8.6.28 Power-on Fault Register
        1. Table 26. Power-on Fault Register Field Descriptions
      29. 8.6.29 PORT RE-MAPPING Register
        1. Table 27. PORT RE-MAPPING Register Field Descriptions
      30. 8.6.30 Port 21 Multi Bit Priority Register
      31. 8.6.31 Port 43 Multi Bit Priority Register
        1. Table 28. Port 43 Register Field Descriptions
      32. 8.6.32 TEMPERATURE Register
        1. Table 29. TEMPERATURE Register Field Descriptions
      33. 8.6.33 INPUT VOLTAGE Register
        1. Table 30. INPUT VOLTAGE Register Field Descriptions
      34. 8.6.34 PORT 1 CURRENT Register
      35. 8.6.35 PORT 2 CURRENT Register
      36. 8.6.36 PORT 3 CURRENT Register
      37. 8.6.37 PORT 4 CURRENT Register
        1. Table 31. PORT 4 CURRENT Register Field Descriptions
      38. 8.6.38 PORT 1 VOLTAGE Register
      39. 8.6.39 PORT 2 VOLTAGE Register
      40. 8.6.40 PORT 3 VOLTAGE Register
      41. 8.6.41 PORT 4 VOLTAGE Register
        1. Table 32. PORT 4 VOLTAGE Register Field Descriptions
      42. 8.6.42 PoE Plus Register
        1. Table 33. PoE Plus Register Field Descriptions
      43. 8.6.43 FIRMWARE REVISION
        1. Table 34. FIRMWARE REVISION Register Field Descriptions
      44. 8.6.44 I2C WATCHDOG Register
        1. Table 35. I2C WATCHDOG Register Field Descriptions
      45. 8.6.45 DEVICE ID Register
        1. Table 36. DEVICE ID Register Field Descriptions
      46. 8.6.46 PORT 1 DETECT RESISTANCE Register
      47. 8.6.47 PORT 2 DETECT RESISTANCE Register
      48. 8.6.48 PORT 3 DETECT RESISTANCE Register
      49. 8.6.49 PORT 4 DETECT RESISTANCE Register
        1. Table 37. PORT 4 DETECT RESISTANCE Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Introduction to PoE
      2. 9.1.2 TPS2388 Application
      3. 9.1.3 Kelvin Current Sensing Resistor
      4. 9.1.4 Connections on Unused Ports
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Pin Bypass Capacitors
        2. 9.2.2.2 Per Port Components
        3. 9.2.2.3 System Level Components (not shown in the schematic diagrams)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VPWR
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Port Current Kelvin Sensing
    2. 11.2 Layout Example
      1. 11.2.1 Component Placement and Routing Guidelines
        1. 11.2.1.1 Power Pin Bypass Capacitors
        2. 11.2.1.2 Per-Port Components
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

–40°C ≤ TJ ≤ 125°C unless otherwise noted. VVDD = 3.3 V, VVPWR = 48 V, VDGND = VAGND, DGND, KSENSA, KSENSB, KSENSC, and KSENSD connected to AGND, and all outputs are unloaded, unless otherwise noted. PoEPn = 0. Positive currents are into pins. RS = 0.255 Ω, to KSENSA (SEN1 or SEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to KSENSD (SEN7 or SEN8). Typical values are at 25°C. All voltages are with respect to AGND, unless otherwise noted. Operating registers loaded with default values, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT SUPPLY VPWR
IVPWR VPWR current consumption VVPWR = 50 V 10 12.5 mA
VVPWR < 8 V 100 µA
VUVLOPW_F VPWR UVLO falling threshold 14.5 17.5 V
VUVLOPW_R VPWR UVLO rising threshold 15.5 18.5 V
VPUV_F VPWR undervoltage falling threshold VPUV threshold 25 26.5 28 V
TOTAL DEVICE POWER DISSIPATION
PT VPWR and VDD consumption VVPWR = 50 V 0.67 W
INPUT SUPPLY VDD
IVDD VDD Current consumption 6 12 mA
VUVDD_F VDD UVLO falling threshold For port deassertion 2.1 2.25 2.4 V
VUVDD_R VDD UVLO rising threshold 2.45 2.6 2.75 V
VUVDD_HYS Hysteresis VDD UVLO 0.35 V
VUVW_F VDD UVLO warning threshold 2.6 2.8 3.0 V
DETECTION
IDISC Detection current First detection point, VVPWR – VDRAINn = 0 V 145 160 190 µA
Second detection point, VVPWR – VDRAINn = 0 V 235 270 300
High-current detection point, VVPWR – VDRAINn = 0 V 490 540 585
Vdetect Open-circuit detection voltage VVPWR – VDRAINn 23.5 26 29 V
RREJ_LOW Rejected resistance low range 0.86 15 kΩ
RREJ_HI Rejected resistance high range 33 100 kΩ
RACCEPT Accepted resistance range 19 25 26.5 kΩ
RSHORT Shorted port threshold 360 Ω
ROPEN Open port threshold 400 kΩ
CLASSIFICATION
VCLASS Classification voltage VVPWR – VDRAINn, VSENn ≥ 0 mV,
Iport ≥ 180 µA		 15.5 18.5 20.5 V
ICLASS_Lim Classification current limit VVPWR – VDRAINn = 0 V 65 75 90 mA
ICLASS_TH Classification threshold current Class 0-1 5 8 mA
Class 1-2 13 16 mA
Class 2-3 21 25 mA
Class 3-4 31 35 mA
Class 4-Class overcurrent 45 51 mA
VMARK Mark voltage 4 mA ≥ Iport ≥ 180 µA, VVPWR – VDRAINn 7 10 V
IMARK_Lim Mark sinking current limit VVPWR – VDRAINn = 0 V 10 70 90 mA
GATE
VGOH Gate drive voltage VGATEn , IGATE = –1 µA 10 12.5 V
IGO- Gate sinking current with Power-on Reset, OSS detected or port turn off command VGATEn = 5 V 60 100 190 mA
IGO short– Gate sinking current with port short-circuit VGATEn = 5 V, VSENn ≥ Vshort (or Vshort2X if 2X mode) 60 100 190 mA
IGO+ Gate sourcing current VGATEn = 0V 39 50 63 µA
DRAIN INPUT
VPGT Power Good threshold Measured at VDRAINn 1.0 2.13 3 V
VSHT Shorted FET threshold Measured at VDRAINn 4 6 8 V
RDRAIN Resistance from DRAINn to VPWR Any operating mode except during detection or while the port is ON, including in device RESET state 80 100 190 kΩ
IDRAIN DRAINn pin bias current VVPWR – VDRAINn = 30 V, port ON 75 120 µA
A/D CONVERTER
tCONV Conversion time, current measurement All ranges, each port 0.64 0.8 0.96 ms
tCONV_V Conversion time, voltage measurement All ranges, each port 0.82 1.03 1.2 ms
tGAP Gap between adjacent current measurement integrations 5% × tCONV ms
Gap between adjacent current averaged results 5% × tINT_CUR ms
ADCBW ADC integration bandwidth (–3 db) Current measurement 320 Hz
tINT_CUR Integration (averaging) time, current Each port, port ON current 82 102 122 ms
tINT_DET Integration (averaging) time, detection 13.1 16.6 20 ms
tINT_portV Integration (averaging) time, port voltage Port powered 3.25 4.12 4.9 ms
tINT_inV Integration (averaging) time, input voltage 3.25 4.12 4.9 ms
Powered port voltage conversion scale factor and accuracy At VVPWR – VDRAINn = 57 V 15097 15565 16032 Counts
At VVPWR – VDRAINn = 44 V 11654 12015 12375 Counts
Powered port current conversion scale factor and accuracy At port current = 770 mA 12363 12616 12868 Counts
At port current = 7.5 mA 100 123 150 Counts
Input voltage conversion scale factor and accuracy At VVPWR = 57 V 15175 15565 15955 Counts
At VVPWR = 44 V 11713 12015 12316 Counts
δV/Vport Voltage reading accuracy At 44 to 57 V –3% 3%
σV Voltage reading repeatability Full scale reading –18 18 mV
δI/Iport Current reading accuracy At 50 mA –3% 3%
At 770 mA -2% 2%
σI Current reading repeatability Full scale reading –7.5 7.5 mA
δR/Rport Resistance reading accuracy 15 kΩ ≤ Rport ≤ 33 kΩ, Cport ≤ 0.25 µF, at 44 to 57 V –7% 7%
PORT CURRENT SENSE
VCUT ICUT limit VDRAINn = 0 V, POL(3:0) = 0001b 9.6 10.2 10.8 mV
VDRAINn = 0 V, POL(3:0) = 0010b 14.53 15.3 16.06
VDRAINn = 0 V, POL(3:0) = 0111b 38.76 40.8 42.84
VDRAINn = 0 V, POL(3:0) = 1111b 77.5 81.6 85.6
VDRAINn = 0 V, POL(3:0) = 0000b,
PoEPn = 1		 77.5 81.6 85.6
VDRAINn = 0 V, POL(3:0) = 1111b,
PoEPn = 1		 222.8 234.6 246.3
δV/Vpolice Police setting resolution –6.3% 6.3%
δicut/ICUT ICUT tolerance All settings except POL(3:0) = 0000b
and 0001b while PoEPn = 0		 –5% 5%
VInrush IInrush limit, 1x or 2x mode VVPWR – VDRAINn = 1 V 10 23 31 mV
VVPWR – VDRAINn = 10 V 20 33 46
VVPWR – VDRAINn = 30 V 102 114.7
VVPWR – VDRAINn = 55 V 102 114.7
VLIM ILIM limit in 1x mode VDRAINn = 1 V 102 114.7 mV
VDRAINn = 13 V 102 114.7
VDRAINn = 30 V 15 23 31
VDRAINn = 48 V 15 23 31
VLIM2X ILIM limit in 2X mode (PoEPn = 1) VDRAINn = 1 V 260 270.3 285 mV
VDRAINn = 10 V 127 140 153
VDRAINn = 30 V 15 23 31
VDRAINn = 48 V 15 23 31
Vshort Ishort threshold in 1X mode and during inrush Threshold for GATE to be less than 1 V,
2 µS after application of pulse		 234 306 mV
Vshort2X Ishort threshold in 2X mode 357 408
Ibias Sense pin bias current Port ON or during class –2.5 0 µA
VIMIN DC disconnect threshold 1.275 2.55 mV
DIGITAL INTERFACE AT VVDD = 3.3 V
VIH Digital input high 2.1 V
VIL Digital input low 0.9 V
VIT_HYS Input voltage hysteresis (SCL, SDAI, A1-A4, RESET, OSS) 0.17 V
VOL Digital output Low, SDAO At 9 mA 0.4 V
Digital output Low, INT At 3 mA 0.4 V
Rpullup Pullup resistor to VDD RESET, A1-A4, TEST0 30 50 80 kΩ
Rpulldown Pulldown resistor to DGND OSS 30 50 80 kΩ
TEST1, 2 30 50 80
THERMAL SHUTDOWN
TSD Shutdown temperature Temperature rising 135 146 °C
Hysteresis 7 °C