SLUSC25A February 2015 – August 2017 TPS2388
PRODUCTION DATA.
COMMAND = 12h with 1 Data Byte, Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P4M1 | P4M0 | P3M1 | P3M0 | P2M1 | P2M0 | P1M1 | P1M0 |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description | ||||
---|---|---|---|---|---|---|---|---|
- | P4M1–P4M0 P3M1–P3M0 P2M1–P2M0 P1M1–P1M0 |
R/W | 0 | Each pair of bits configures the operating mode per port. The selection is as following: |
||||
M1 | M0 | Operating Mode | ||||||
0 | 0 | OFF | ||||||
0 | 1 | Manual | ||||||
1 | 0 | Semiauto | ||||||
1 | 1 | Semiauto | ||||||
In OFF mode, the port is OFF and there is no detection nor classification. In Manual mode, there is no automatic state change. In semiauto mode, detection and class are automated but not the port power on. Note that while in OFF mode, the corresponding bits are cleared: Detection Event register (CLSCn, DETCn), Fault Event register (DISFn, ICUTn), Start Event register (STRTn), Port n Status register (CLASS Pn, DETECT Pn), Detect/Class Enable register (CLEn, DETEn) and Power-on Fault register (PFn). The corresponding PEn and PGn bits of Power Status Register are also updated accordingly. The corresponding PGCn and PECn bits of Power Event register will also be set if there is a change. Also, a change of mode from semiauto to manual mode or OFF mode will cancel any ongoing cooldown time period. |