SLUSC25A February 2015 – August 2017 TPS2388
PRODUCTION DATA.
COMMAND = 19h with 1 Data Byte, Write Only
Push button register.
Used to force a port(s) turn on or turn off in any mode except OFF mode. If TPON bit in the PoE Plus register is low, or if the PSE controller is configured in Manual mode, writing a 1 at that PWONn bit location will immediately turn on the associated port, regardless of the classification and detection status and regardless of the IEEE802.3 TPON timing specification. This is also the case if TPON is set and DETn bit is 0, in semiauto mode.
If TPON bit in the PoE Plus register is set, and DETn bit (DETECT/CLASS ENABLE register) is set and while in semiauto mode, writing a 1 at a PWONn bit will turn on the associated port but only if the IEEE802.3 TPON timing specification can be met and if the detection is valid (and class is valid if enabled). TPON specification is the time from the completion of a valid detection cycle to port turn ON.
If TPON specification cannot be met, a new detection cycle is restarted, followed by a classification cycle if enabled, at the end of which the port is turned on, but only if a valid detection is returned and the IEEE802.3 TPON specification can be met. For this case, there is no additional attempt to turn on the port until this push button is reasserted. If the last detection result is not valid, the port is not turned on.
Note that in semiauto, as long as the port is kept off, detection and classification are performed continuously, if the corresponding class and detect enable bits are set.
Writing a 1 at POFFn location turns off the associated port.
Note that writing a 1 at POFFn and PWONn of same port during the same write operation turns the port off.
Also note that tOVLD, tLIM, tSTART, and disconnect events have priority over the power on command. During tOVLD, tLIM, or tSTART cool down cycle, any port turn on using Power Enable command will be ignored and the port will be kept off.
Turning OFF a port with this command also clears the corresponding bits in Detection Event register (CLSCn, DETCn), Fault Event register (DISFn, ICUTn), Start Event register (STRTn, ILIMn), Port n Status register (CLASS Pn, DETECT Pn), DETECT/CLASS ENABLE register (CLEn, DETEn) and Power-on Fault register (PFn). The corresponding PGCn and PECn bits of Power Event register will also be set if there is a change. The corresponding PEn and PGn bits of Power Status Register are also updated accordingly.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POFF4 | POFF3 | POFF2 | POFF1 | PWON4 | PWON3 | PWON2 | PWON1 |
W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 |
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7–4 | POFF4–POFF1 | W | 0 | Port power off bits |
3–0 | PWON4–PWON1 | W | 0 | Port power on bits |