SLUSD53G
March 2018 – August 2020
TPS23880
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
6.1
Detailed Pin Description
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Parameter Measurement Information
8.1
Timing Diagrams
9
Detailed Description
9.1
Overview
9.1.1
Operating Modes
9.1.1.1
Auto
9.1.1.2
Semiauto
9.1.1.3
Manual/Diagnostic
9.1.1.4
Power Off
9.1.2
PoE Compliance Terminology
9.1.3
Channel versus Port Terminology
9.1.4
Requested Class versus Assigned Class
9.1.5
Power Allocation and Power Demotion
9.1.6
Programmable SRAM
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Port Remapping
9.3.2
Port Power Priority
9.3.3
Analog-to-Digital Converters (ADC)
9.3.4
I2C Watchdog
9.3.5
Current Foldback Protection
9.4
Device Functional Modes
9.4.1
Detection
9.4.2
Connection Check
9.4.3
Classification
9.4.4
DC Disconnect
9.5
I2C Programming
9.5.1
I2C Serial Interface
9.6
Register Maps
9.6.1
Complete Register Set
9.6.2
Detailed Register Descriptions
9.6.2.1
INTERRUPT Register
9.6.2.2
INTERRUPT MASK Register
9.6.2.3
POWER EVENT Register
9.6.2.4
DETECTION EVENT Register
9.6.2.5
FAULT EVENT Register
9.6.2.6
START/ILIM EVENT Register
9.6.2.7
SUPPLY and FAULT EVENT Register
9.6.2.7.1
Detected SRAM Faults and "Safe Mode"
9.6.2.8
CHANNEL 1 DISCOVERY Register
9.6.2.9
CHANNEL 2 DISCOVERY Register
9.6.2.10
CHANNEL 3 DISCOVERY Register
9.6.2.11
CHANNEL 4 DISCOVERY Register
9.6.2.12
POWER STATUS Register
9.6.2.13
PIN STATUS Register
9.6.2.14
OPERATING MODE Register
9.6.2.15
DISCONNECT ENABLE Register
9.6.2.16
DETECT/CLASS ENABLE Register
9.6.2.17
Power Priority / 2Pair PCUT Disable Register Name
9.6.2.18
TIMING CONFIGURATION Register
9.6.2.19
GENERAL MASK Register
9.6.2.20
DETECT/CLASS RESTART Register
9.6.2.21
POWER ENABLE Register
9.6.2.22
RESET Register
9.6.2.23
ID Register
9.6.2.24
Connection Check and Auto Class Status Register
9.6.2.25
2-Pair Police Ch-1 Configuration Register
9.6.2.26
2-Pair Police Ch-2 Configuration Register
9.6.2.27
2-Pair Police Ch-3 Configuration Register
9.6.2.28
2-Pair Police Ch-4 Configuration Register
9.6.2.29
Power-on Fault Register
9.6.2.30
PORT RE-MAPPING Register
9.6.2.31
Channels 1 and 2 Multi Bit Priority Register
9.6.2.32
Channels 3 and 4 Multi Bit Priority Register
9.6.2.33
4-Pair Wired and Port Power Allocation Register
9.6.2.34
4-Pair Police Ch-1 and 2 Configuration Register
9.6.2.35
4-Pair Police Ch-3 and 4 Configuration Register
9.6.2.36
TEMPERATURE Register
9.6.2.37
4-Pair Fault Configuration Register
9.6.2.38
INPUT VOLTAGE Register
9.6.2.39
CHANNEL 1 CURRENT Register
9.6.2.40
CHANNEL 2 CURRENT Register
9.6.2.41
CHANNEL 3 CURRENT Register
9.6.2.42
CHANNEL 4 CURRENT Register
9.6.2.43
CHANNEL 1 VOLTAGE Register
9.6.2.44
CHANNEL 2 VOLTAGE Register
9.6.2.45
CHANNEL 3 VOLTAGE Register
9.6.2.46
CHANNEL 4 VOLTAGE Register
9.6.2.47
2x FOLDBACK SELECTION Register
95
9.6.2.48
FIRMWARE REVISION Register
9.6.2.49
I2C WATCHDOG Register
9.6.2.50
DEVICE ID Register
9.6.2.51
CHANNEL 1 DETECT RESISTANCE Register
9.6.2.52
CHANNEL 2 DETECT RESISTANCE Register
9.6.2.53
CHANNEL 3 DETECT RESISTANCE Register
9.6.2.54
CHANNEL 4 DETECT RESISTANCE Register
9.6.2.55
CHANNEL 1 ASSIGNED CLASS Register
9.6.2.56
CHANNEL 2 ASSIGNED CLASS Register
9.6.2.57
CHANNEL 3 ASSIGNED CLASS Register
9.6.2.58
CHANNEL 4 ASSIGNED CLASS Register
9.6.2.59
AUTO CLASS CONTROL Register
9.6.2.60
CHANNEL 1 AUTO CLASS POWER Register
9.6.2.61
CHANNEL 2 AUTO CLASS POWER Register
9.6.2.62
CHANNEL 3 AUTO CLASS POWER Register
9.6.2.63
CHANNEL 4 AUTO CLASS POWER Register
9.6.2.64
ALTERNATIVE FOLDBACK Register
9.6.2.65
SRAM CONTROL Register
9.6.2.65.1
SRAM START ADDRESS (LSB) Register
9.6.2.65.2
SRAM START ADDRESS (MSB) Register
9.6.2.65.3
116
10
Application and Implementation
10.1
Application Information
10.1.1
Introduction to PoE
10.1.1.1
2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Connections on Unused Channels
10.2.2.2
Power Pin Bypass Capacitors
10.2.2.3
Per Port Components
10.2.2.4
System Level Components (not shown in the schematic diagrams)
10.2.3
Application Curves
11
Power Supply Recommendations
11.1
VDD
11.2
VPWR
12
Layout
12.1
Layout Guidelines
12.1.1
Kelvin Current Sensing Resistors
12.2
Layout Example
12.2.1
Component Placement and Routing Guidelines
12.2.1.1
Power Pin Bypass Capacitors
12.2.1.2
Per-Port Components
13
Device and Documentation Support
13.1
Documentation Support
13.1.1
Related Documentation
13.2
Receiving Notification of Documentation Updates
13.3
Support Resources
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTQ|56
MPQF168D
Thermal pad, mechanical data (Package|Pins)
RTQ|56
QFND490A
Orderable Information
slusd53g_oa
slusd53g_pm
9.6.2
Detailed Register Descriptions