SLUSD53G March 2018 – August 2020 TPS23880
PRODUCTION DATA
COMMAND = 01h with 1 Data Byte, Read/Write
Each bit corresponds to a particular event or fault as defined in the Interrupt register.
Writing a 0 into a bit will mask the corresponding event/fault from activating the INT output.
Note that the bits of the Interrupt register always change state according to events or faults, regardless of the state of the state of the Interrupt Mask register.
Note that the INTEN bit of the General Mask register must also be set in order to allow an event to activate the INT output.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SUMSK | STMSK | IFMSK | CLMSK | DEMSK | DIMSK | PGMSK | PEMSK |
R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SUMSK | R/W | 1 | Supply Event Fault mask bit.
1 = Supply Event Fault will activate the INT output. 0 = Supply Event Fault will have no impact on INT output. |
6 | STMSK | R/W | 0 | tSTART Fault mask bit.
1 = tSTART Fault will activate the INT output. 0 = tSTART Fault will have no impact on INT output. |
5 | IFMSK | R/W | 0 | tOVLD or tLIM Fault mask bit.
1 = tOVLD and/or tLIM Fault occurrence will activate the INT output 0 = tOVLD and/or tLIM Fault occurrence will have no impact on INT output |
4 | CLMSK | R/W | 0 | Classification cycle mask bit.
1 = Classification cycle occurrence will activate the INT output. 0 = Classification cycle occurrence will have no impact on INT output. |
3 | DEMSK | R/W | 0 | Detection cycle mask bit.
1 = Detection cycle occurrence will activate the INT output. 0 = Detection cycle occurrence will have no impact on INT output. |
2 | DIMSK | R/W | 0 | Disconnect event mask bit.
1 = Disconnect event occurrence will activate th INT output. 0 = Disconnect event occurrence will have no impact on INT output. |
1 | PGMSK | R/W | 0 | Power good status change mask bit.
1 = Power good status change will activate the INT output. 0 = Power good status change will have no impact on INT output. |
0 | PEMSK | R/W | 0 | Power enable status change mask bit.
1 = Power enable status change will activate the INT output. 0 = Power enable status change will have no impact on INT output. |