SLVSF02E march   2019  – may 2023 TPS23881

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Detailed Pin Description
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  10. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Semiauto
        3. 9.1.1.3 Manual and Diagnostic
        4. 9.1.1.4 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 Channel versus Port Terminology
      4. 9.1.4 Requested Class versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Connection Check
      3. 9.4.3 Classification
      4. 9.4.4 DC Disconnect
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
        2. 9.6.2.2  INTERRUPT MASK Register
        3. 9.6.2.3  POWER EVENT Register
        4. 9.6.2.4  DETECTION EVENT Register
        5. 9.6.2.5  FAULT EVENT Register
        6. 9.6.2.6  START/ILIM EVENT Register
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
            1. 9.6.2.7.1.1 ULA (Ultra Low Alpha) Package Option: TPS23881A
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
        12. 9.6.2.12 POWER STATUS Register
        13. 9.6.2.13 PIN STATUS Register
        14. 9.6.2.14 OPERATING MODE Register
        15. 9.6.2.15 DISCONNECT ENABLE Register
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
        18. 9.6.2.18 TIMING CONFIGURATION Register
        19. 9.6.2.19 GENERAL MASK Register
        20. 9.6.2.20 DETECT/CLASS RESTART Register
        21. 9.6.2.21 POWER ENABLE Register
        22. 9.6.2.22 RESET Register
        23. 9.6.2.23 ID Register
        24. 9.6.2.24 Connection Check and Auto Class Status Register
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
        29. 9.6.2.29 Capacitance (Legacy PD) Detection
        30. 9.6.2.30 Power-on Fault Register
        31. 9.6.2.31 PORT RE-MAPPING Register
        32. 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
        34. 9.6.2.34 4-Pair Wired and Port Power Allocation Register
        35. 9.6.2.35 4-Pair Police Ch-1 and 2 Configuration Register
        36. 9.6.2.36 4-Pair Police Ch-3 and 4 Configuration Register
        37. 9.6.2.37 TEMPERATURE Register
        38. 9.6.2.38 4-Pair Fault Configuration Register
        39. 9.6.2.39 INPUT VOLTAGE Register
        40. 9.6.2.40 CHANNEL 1 CURRENT Register
        41. 9.6.2.41 CHANNEL 2 CURRENT Register
        42. 9.6.2.42 CHANNEL 3 CURRENT Register
        43. 9.6.2.43 CHANNEL 4 CURRENT Register
        44. 9.6.2.44 CHANNEL 1 VOLTAGE Register
        45. 9.6.2.45 CHANNEL 2 VOLTAGE Register
        46. 9.6.2.46 CHANNEL 3 VOLTAGE Register
        47. 9.6.2.47 CHANNEL 4 VOLTAGE Register
        48. 9.6.2.48 2x FOLDBACK SELECTION Register
        49. 9.6.2.49 FIRMWARE REVISION Register
        50. 9.6.2.50 I2C WATCHDOG Register
        51. 9.6.2.51 DEVICE ID Register
        52. 9.6.2.52 CHANNEL 1 DETECT RESISTANCE Register
        53. 9.6.2.53 CHANNEL 2 DETECT RESISTANCE Register
        54. 9.6.2.54 CHANNEL 3 DETECT RESISTANCE Register
        55. 9.6.2.55 CHANNEL 4 DETECT RESISTANCE Register
        56. 9.6.2.56 CHANNEL 1 DETECT CAPACITANCE Register
        57. 9.6.2.57 CHANNEL 2 DETECT CAPACITANCE Register
        58. 9.6.2.58 CHANNEL 3 DETECT CAPACITANCE Register
        59. 9.6.2.59 CHANNEL 4 DETECT CAPACITANCE Register
        60. 9.6.2.60 CHANNEL 1 ASSIGNED CLASS Register
        61. 9.6.2.61 CHANNEL 2 ASSIGNED CLASS Register
        62. 9.6.2.62 CHANNEL 3 ASSIGNED CLASS Register
        63. 9.6.2.63 CHANNEL 4 ASSIGNED CLASS Register
        64. 9.6.2.64 AUTO CLASS CONTROL Register
        65. 9.6.2.65 CHANNEL 1 AUTO CLASS POWER Register
        66. 9.6.2.66 CHANNEL 2 AUTO CLASS POWER Register
        67. 9.6.2.67 CHANNEL 3 AUTO CLASS POWER Register
        68. 9.6.2.68 CHANNEL 4 AUTO CLASS POWER Register
        69. 9.6.2.69 ALTERNATIVE FOLDBACK Register
        70. 9.6.2.70 SRAM CONTROL Register
          1. 9.6.2.70.1 SRAM START ADDRESS (LSB) Register
          2. 9.6.2.70.2 SRAM START ADDRESS (MSB) Register
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Introduction to PoE
        1. 10.1.1.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not Shown in the Schematic Diagrams)
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.2.14 OPERATING MODE Register

COMMAND = 12h with 1 Data Byte, Read/Write

Figure 9-21 OPERATING MODE Register Format
76543210
C4M1C4M0C3M1C3M0C2M1C2M0C1M1C1M0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-16 OPERATING MODE Register Field Descriptions
Bit Field Type Reset Description
7-0 CnM1–CnM0 R/W 0 Each pair of bits configures the operating mode per channel.

The selection is as following:
M1 M0 Operating Mode
0 0 OFF
0 1 Diagnostic/Manual
1 0 Semiauto
1 1 Auto

For a 4-pair wired port, both channels must be set to the same operating mode. Otherwise, the port will not conduct discovery, and any turn on commands will be ignored.

OFF MODE:

In OFF mode, the Channel is OFF and neither detection nor classification is performed independent of the DETE, CLSE or PWON bits.

The table below depicts what bits will be cleared when a channel is changed to OFF mode from any other operating mode:

Table 9-17 Transition to OFF Mode
RegisterBits to be reset
0x04CLSCn and DETCn
0x06DISFn and PCUTn
0x08STRTn and ILIMn
0x0A/BPCUTnn
0x0C-0FRequested Class and Detection
0x10PGn and PEn
0x14CLEn and DETEn
0x1CACn and CCnn
0x1E-212P Policing set to 0xFFh
0x24PFn
0x2A-2B4P Policing set to 0xFFh
0x2DNLMnn, NCTnn, 4PPCTnn, and DCDTnn
0x30-3FChannel Voltage and Current Measurements
0x402xFBn
0x44 - 47Detection Resistance Measurements
0x4C-4FAssigned Class and Previous Class
0x51-54Autoclass Measurement

Note:

it may take upwards of 5 ms before all of the registers are cleared following a change to OFF mode.

Only the bits associated with the channel/port ("n") being set into OFF mode will be cleared. Those bits associated with channels/ports remaining in operation will not be changed.

In the event either the PGn or PEn bits were changed from a 1 to a zero, the corresponding PGCn and PECn bits will be set in the POWER EVENT register 0x02h.

Also, a change of mode from semiauto to manual/diagnostic mode or OFF mode will cancel any ongoing cooldown time period.

DIAGNOSTIC/MANUAL MODE:

In Manual/Diagnostic mode, there is no automatic state change. The channel remains idle until DETE, CLSE (0x14h or 0x18h), or PWON command is provided. Upon the setting of the DETE and/or CLSE bits, the channel will perform a singular detection and/or classification cycle on the corresponding channel.

Note:

Setting a PWONn bit in register 0x19 results in the immediate turn on of that channel.

There is no Assigned Class assigned for ports/channels powered out of Manual/Diagnostic mode. Any settings such as the port power policing and 1x/2x foldback selection that are typically configure based on the assigned class result need to manually configured by the user.

For 4-Pair wired ports (4PWnn bit in 0x29 = 1):

Setting the DETE or CLSE bits on only one channel will result in detection and/or classification only being done on that channel, and Connection Check will not be preformed.

Setting the DETE bits for both channels during the same I2C operation will result in detection cycles being completed on both channels, and if the detection results are valid, connection check will also be completed.

Setting the CLSE bits for both channels during the same I2C operation will result in staggered classification measurements being done on both channels

Note:

Setting a PWONn bit in register 0x19 results in the immediate turn on of that channel.

Note:

DC Disconnect for 4-Pair ports power on in Manual/Diagnostic mode will behave as independent channels. Thus, if either channel current falls below VIMIN for longer than tMPDO , that channel will be disabled and a disconnect fault will be set (DISFn bits in register 0x06/7).

Table 9-18 Channel Behavior in Diagnostic/Manual Mode
CLEnDETnPWONnChannel Operation
000Idle
010Single Detection measurement (Connection check completed if 4P wired and DETE bits are set for both channels)
100Single Classification measurement
110Single Detection and Classification measurement done. (Connection check completed if 4P wired and both DETE and CLE bits are set for both channels)
--1Channel immediate turns on without any detection or classification being performed

SEMI AUTO MODE:

In Semi Auto mode, as long as the Channel is unpowered, detection and classifications may be performed continuously depending if the corresponding class and detect enable bits are set (register 0x14h).

Table 9-19 Channel Behavior in Semi Auto Mode
CLEnDETnChannel Operation
00Idle
01Cycling Detection Measurements only
10Idle
11Cycling Detection and Classification Measurements
Note:

If two channels are configured as a 4-pair wired port, a connection check measurement will be performed once a valid detection result is seen on one of the channel

For a 4-Pair Dual Signature PD that has only one channel powered, the unpowered channel will resume detect and class provided the DETE and CLE bits are set for that channel in 0x14h.

AUTO MODE:

In Auto mode, channels will automatically power on any valid detection and classification signature based on the Port Power Allocation settings in 0x29. The channels will remain idle until DETE and CLSE (0x14 or 0x18) are set, or a PWON command is given.

Prior to setting DETE and CLE or sending a PWON command in AUTO mode, the following registers need to be configured according to the system requirements and configuration:

RegisterBits
0x26Port Re-mapping
0x294-Pair Wired and Port Power Allocation
0x50Auto AC Enable
0x55Alternative Inrush and Powered Foldback Enable
Note:

Changes to these registers after the DETE and CLE bits are set in Auto mode may result in undesired or non IEEE complaint operation.

The following registers may be configured or changed after turn on if changes to the default operation are desired as these values are internally set during power on based on the port configuration and resulting assigned PD class:

RegisterBits
0x1E-212-Pair Policing
0x2A-2B4-Pair Policing
0x2D4P Pcut Enable and DC Disconnect Threshold bits
0x402x Foldback Enable