SLVSF02E march   2019  – may 2023 TPS23881

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Detailed Pin Description
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  10. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Semiauto
        3. 9.1.1.3 Manual and Diagnostic
        4. 9.1.1.4 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 Channel versus Port Terminology
      4. 9.1.4 Requested Class versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Connection Check
      3. 9.4.3 Classification
      4. 9.4.4 DC Disconnect
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
        2. 9.6.2.2  INTERRUPT MASK Register
        3. 9.6.2.3  POWER EVENT Register
        4. 9.6.2.4  DETECTION EVENT Register
        5. 9.6.2.5  FAULT EVENT Register
        6. 9.6.2.6  START/ILIM EVENT Register
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
            1. 9.6.2.7.1.1 ULA (Ultra Low Alpha) Package Option: TPS23881A
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
        12. 9.6.2.12 POWER STATUS Register
        13. 9.6.2.13 PIN STATUS Register
        14. 9.6.2.14 OPERATING MODE Register
        15. 9.6.2.15 DISCONNECT ENABLE Register
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
        18. 9.6.2.18 TIMING CONFIGURATION Register
        19. 9.6.2.19 GENERAL MASK Register
        20. 9.6.2.20 DETECT/CLASS RESTART Register
        21. 9.6.2.21 POWER ENABLE Register
        22. 9.6.2.22 RESET Register
        23. 9.6.2.23 ID Register
        24. 9.6.2.24 Connection Check and Auto Class Status Register
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
        29. 9.6.2.29 Capacitance (Legacy PD) Detection
        30. 9.6.2.30 Power-on Fault Register
        31. 9.6.2.31 PORT RE-MAPPING Register
        32. 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
        34. 9.6.2.34 4-Pair Wired and Port Power Allocation Register
        35. 9.6.2.35 4-Pair Police Ch-1 and 2 Configuration Register
        36. 9.6.2.36 4-Pair Police Ch-3 and 4 Configuration Register
        37. 9.6.2.37 TEMPERATURE Register
        38. 9.6.2.38 4-Pair Fault Configuration Register
        39. 9.6.2.39 INPUT VOLTAGE Register
        40. 9.6.2.40 CHANNEL 1 CURRENT Register
        41. 9.6.2.41 CHANNEL 2 CURRENT Register
        42. 9.6.2.42 CHANNEL 3 CURRENT Register
        43. 9.6.2.43 CHANNEL 4 CURRENT Register
        44. 9.6.2.44 CHANNEL 1 VOLTAGE Register
        45. 9.6.2.45 CHANNEL 2 VOLTAGE Register
        46. 9.6.2.46 CHANNEL 3 VOLTAGE Register
        47. 9.6.2.47 CHANNEL 4 VOLTAGE Register
        48. 9.6.2.48 2x FOLDBACK SELECTION Register
        49. 9.6.2.49 FIRMWARE REVISION Register
        50. 9.6.2.50 I2C WATCHDOG Register
        51. 9.6.2.51 DEVICE ID Register
        52. 9.6.2.52 CHANNEL 1 DETECT RESISTANCE Register
        53. 9.6.2.53 CHANNEL 2 DETECT RESISTANCE Register
        54. 9.6.2.54 CHANNEL 3 DETECT RESISTANCE Register
        55. 9.6.2.55 CHANNEL 4 DETECT RESISTANCE Register
        56. 9.6.2.56 CHANNEL 1 DETECT CAPACITANCE Register
        57. 9.6.2.57 CHANNEL 2 DETECT CAPACITANCE Register
        58. 9.6.2.58 CHANNEL 3 DETECT CAPACITANCE Register
        59. 9.6.2.59 CHANNEL 4 DETECT CAPACITANCE Register
        60. 9.6.2.60 CHANNEL 1 ASSIGNED CLASS Register
        61. 9.6.2.61 CHANNEL 2 ASSIGNED CLASS Register
        62. 9.6.2.62 CHANNEL 3 ASSIGNED CLASS Register
        63. 9.6.2.63 CHANNEL 4 ASSIGNED CLASS Register
        64. 9.6.2.64 AUTO CLASS CONTROL Register
        65. 9.6.2.65 CHANNEL 1 AUTO CLASS POWER Register
        66. 9.6.2.66 CHANNEL 2 AUTO CLASS POWER Register
        67. 9.6.2.67 CHANNEL 3 AUTO CLASS POWER Register
        68. 9.6.2.68 CHANNEL 4 AUTO CLASS POWER Register
        69. 9.6.2.69 ALTERNATIVE FOLDBACK Register
        70. 9.6.2.70 SRAM CONTROL Register
          1. 9.6.2.70.1 SRAM START ADDRESS (LSB) Register
          2. 9.6.2.70.2 SRAM START ADDRESS (MSB) Register
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Introduction to PoE
        1. 10.1.1.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not Shown in the Schematic Diagrams)
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.2.21 POWER ENABLE Register

COMMAND = 19h with 1 Data Byte, Write Only

Push button register.

Used to initiate a channel(s) turn on or turn off in any mode except OFF mode.

Figure 9-28 POWER ENABLE Register Format
7 6 5 4 3 2 1 0
POFF4 POFF3 POFF2 POFF1 PWON4 PWON3 PWON2 PWON1
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
Table 9-28 POWER ENABLE Register Field Descriptions
Bit Field Type Reset Description
7–4 POFF4–POFF1 W 0 Channel power off bits
3–0 PWON4–PWON1 W 0 Channel power on bits

Note:

Writing a “1” at POFFn and PWONn on same Channel during the same write operation turns the Channel off.

Note:

The tOVLD, tLIM, tSTART and disconnect events have priority over the PWON command. During tOVLD, tLIM or tSTART, cool down cycle, any channel turn on using Power Enable command will be ignored and the Channel will be kept off.

Note:

For 4-Pair wired ports:

These bits control the individual Channel response of each Channel. Thus it is recommended that for 4-pair wire ports, the bits for both channels be set simultaneously.

In Semi Auto mode with DETE = CLE = 1 on both channels, it is permissible to set only one PWON bit to attempt to turn on only that singular channel.

For 4P Single Signature devices that classify as class 5-8, a singular PWON command will fail and a STRT fault set with the “insufficient power” code written to 0x24.

If the PD presents itself as class 4 or below, then only that pair set will be powered.

Setting the alternate PWON bit for the secondary channel of a single signature device after the primary is already powered will result in the immediate turn on of the channel without completing DET or CLS.

For a 4-Pair Dual Signature device that has only one channel powered, setting the PWON bit for the unpowered channel will result in a turn on attempt on that channel based on the assigned classification of the other channel and the Power Allocation settings in 0x29h at the time of the new PWON command.

PWONn in Diagnostic/Manual Mode:

If the PSE controller is configured in Diagnostic mode, writing a “1” at that PWONn bit location will immediately turn on the associated Channel.

PWONn in Semi Auto Mode:

While in Semi Auto mode, writing a “1” at a PWONn bit will attempt to turn on the associated Channel. If the detection or class results are invalid, the Channel is not turned on, and there will be no additional attempts to turn on the Channel until this push button is reasserted and the channel will resume its configured semi auto mode operation.

Note:

In Semi Auto mode, the Power Allocation (0x29h) value needs to be set prior to issuing a PWON command. Any changes to the Power Allocation value after a PWON command is given may be ignored.

Table 9-29 Channel Response to PWONn Command in Semi Auto Mode
CLEn DETEn Channel Operation Result of PWONn Command
0 0 Idle Singular Turn On attempted with Full DET and CLS cycle
0 1 Cycling Detection Measurements only Singular Turn On attempted with Full DET and CLS cycle
1 0 Idle Singular Turn On attempted with Full DET and CLS cycle
1 1 Cycling Detection and Classification Measurements Singular Turn On attempted after next (or current) DET and CLS cycle

In semi auto mode with DETE and CLE set, as long as the PWONx command is received prior to the start of classification, the Channel will be powered immediately after classification is complete provided the classification result is valid and the power allocations settings (see register 0x29h) are sufficient to enable power on.

PWONn in Auto Mode:

In Auto mode with DETE or CLE set to 0, a PWONx command will initiate a singular detection and classification cycle and the port/channel will be powered immediately after classification is complete provided the classification result is valid and the power allocations settings (see register 0x29h) are sufficient to enable power on.

In Auto mode with DETE and CLE = 1, there is no need for a PWON command. The port/channel will automatically attempt to turn on after each detection and classification cycle.

Note:

In Auto mode, the Power Allocation (0x29h) value needs to be set prior to issuing a PWON command. Any changes to the Power Allocation value after a PWON command is given may be ignored.

A singular PWONn command will be ignored for a 4-Pair wired port in Auto mode.

Table 9-30 Channel Response to PWONn Command in Auto Mode
CLEn DETEn Channel Operation Result of PWONn Command
0 0 Idle Singular Turn On attempted with Full DET and CLS cycle
0 1 Cycling Detection Measurements only Singular Turn On attempted with Full DET and CLS cycle
1 0 Idle Singular Turn On attempted with Full DET and CLS cycle
1 1 Cycling Detection and Classification Measurements NA - Channel will power automatically after a valid detection and classification

PWOFFn in any Mode:

The channel is immediately disabled and the following registers are cleared:

Table 9-31 Channel Turn Off with PWOFFn Command
Register Bits to be Reset
0x04 CLSCn and DETCn
0x06 DISFn and PCUTn
0x08 STRTn and ILIMn
0x0A/B PCUTnn
0x0C-0F Requested Class and Detection
0x10 PGn and PEn
0x14 CLEn and DETEn
0x1C ACn and CCnn
0x1E-21 2P Policing set to 0xFFh
0x24 PFn
0x2A-2B 4P Policing set to 0xFFh
0x2D NLMnn, NCTnn, 4PPCTnn, and DCDTnn
0x30-3F Channel Voltage and Current Measurements
0x40 2xFBn
0x44 - 47 Detection Resistance Measurements
0x4C-4F Assigned Class and Previous Class
0x51-54 Autoclass Measurement
Note:

It may take upwards of 5ms after PWOFFn command for all register values to be updated.

Only the bits associated with the channel/port ("n") with PWOFFn set will be cleared. Those bits associated with channels/ports remaining in operation will not be changed.

These bits control the response of each channel individually. Thus, it is recommended that for 4-pair wire ports, the bits for both channels be set simultaneously.

Note:

If only one channel of a 4-pair single signature load with a Class 5 or higher assigned class is given a PWOFFn command, both channels will be disabled.

In the event a singular channel of a 4-pair dual signature PD is turned off due to a PWOFFn command, the power may be reapplied to that channel by setting the PWON bit in 0x19h provided the detection and classification are still valid and the Power Allocation settings in 0x29 are sufficient based on the assigned classification of the powered channel.