SLVSHI5 Data sheet

SLVSHI5 April 2024 TPS23881B

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RTQ|56
- MPQF168D

Thermal pad, mechanical data (Package|Pins)

RTQ|56
- QFND490A

Orderable Information

8.3.2 Port Power Priority

The TPS23881B supports 1- and 3-bit shutdown priority, which are selected with the MbitPrty bit of General Mask register (0x17).

The 1-bit shutdown priority works with the Port Power Priority (0x15) register. An OSSn bit with a value of 1 indicates that the corresponding port is treated as low priority, while a value of 0 corresponds to a high priority. As soon as the OSS input goes high, the low-priority ports are turned off.

The 3-bit shutdown priority works with the Multi Bit Power Priority (0x27/28) register, which holds the priority settings. A port with “000” code in this register has highest priority. Port priority reduces as the 3-bit value increases, with up to 8 priority levels. See Figure 8-1.

The multi bit port priority implementation is defined as the following:

OSS code ≤ Priority setting (0x27/28 register): Port is disabled
OSS code > Priority setting (0x27/28 register): Port remains active

Figure 8-1 Multi Bit Priority Port Shutdown if Lower-Priority Port

Note:

Prior to setting the MbitPrty bit from 0 to 1, make sure the OSS input is in the idle (low) state for a minimum of 200 µs, to avoid any port misbehavior related to loss of synchronization with the OSS bit stream.

Note:

The OSS input has an internal 1-µs to 5-µs deglitch filter. From the idle state, a pulse with a longer duration is interpreted as a valid start bit. Ensure that the OSS signal is noise free.

Note:

To ensure both channels of a 4-pair port are disabled during and OSS event, make sure both channel have the same configurations in the 0x15 or 0x27/28 registers.