SLVSF21D August 2019 – August 2020 TPS23882
PRODUCTION DATA
COMMAND = 12h with 1 Data Byte, Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
C4M1 | C4M0 | C3M1 | C3M0 | C2M1 | C2M0 | C1M1 | C1M0 |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description | ||||
---|---|---|---|---|---|---|---|---|
7-0 | CnM1–CnM0 | R/W | 0 | Each pair of bits configures
the operating mode per channel. The selection is as following: |
||||
M1 | M0 | Operating Mode | ||||||
0 | 0 | OFF | ||||||
0 | 1 | Diagnostic/Manual | ||||||
1 | 0 | Semiauto | ||||||
1 | 1 | Auto | ||||||
OFF MODE:
In OFF mode, the Channel is OFF and neither detection nor classification is performed independent of the DETE, CLSE or PWON bits.
The table below depicts what bits will be cleared when a channel is changed to OFF mode from any other operating mode:
Register | Bits to be reset |
---|---|
0x04 | CLSCn and DETCn |
0x06 | DISFn and PCUTn |
0x08 | STRTn and ILIMn |
0x0C-0F | Requested Class and Detection |
0x10 | PGn and PEn |
0x14 | CLEn and DETEn |
0x1C | ACn |
0x1E-21 | 2P Policing set to 0xFFh |
0x24 | PFn |
0x30-3F | Channel Voltage and Current Measurements |
0x40 | 2xFBn |
0x44 - 47 | Detection Resistance Measurements |
0x4C-4F | Assigned Class and Previous Class |
0x51-54 | Autoclass Measurement |
it may take upwards of 5 ms before all of the registers are cleared following a change to OFF mode.
Only the bits associated with the channel/port ("n") being set into OFF mode will be cleared. Those bits associated with channels/ports remaining in operation will not be changed.
In the event either the PGn or PEn bits were changed from a 1 to a zero, the corresponding PGCn and PECn bits will be set in the POWER EVENT register 0x02h.
Also, a change of mode from semiauto to manual/diagnostic mode or OFF mode will cancel any ongoing cooldown time period.
DIAGNOSTIC/MANUAL MODE:
In Manual/Diagnostic mode, there is no automatic state change. The channel remains idle until DETE, CLSE (0x14h or 0x18h), or PWON command is provided. Upon the setting of the DETE and/or CLSE bits, the channel will perform a singular detection and/or classification cycle on the corresponding channel.
Setting a PWONn bit in register 0x19 results in the immediate turn on of that channel.
There is no Assigned Class assigned for ports/channels powered out of Manual/Diagnostic mode. Any settings such as the port power policing and 1x/2x foldback selection that are typically configure based on the assigned class result need to manually configured by the user.
Setting a PWONn bit in register 0x19 results in the immediate turn on of that channel.
SEMI AUTO MODE:
In Semi Auto mode, as long as the Channel is unpowered, detection and classifications may be performed continuously depending if the corresponding class and detect enable bits are set (register 0x14h).
CLEn | DETn | Channel Operation |
---|---|---|
0 | 0 | Idle |
0 | 1 | Cycling Detection Measurements only |
1 | 0 | Idle |
1 | 1 | Cycling Detection and Classification Measurements |
AUTO MODE:
In Auto mode, channels will automatically power on any valid detection and classification signature based on the Port Power Allocation settings in 0x29. The channels will remain idle until DETE and CLSE (0x14 or 0x18) are set, or a PWON command is given.
Prior to setting DETE and CLE or sending a PWON command in AUTO mode, the following registers need to be configured according to the system requirements and configuration:
Register | Bits |
---|---|
0x26 | Port Re-mapping |
0x29 | Port Power Allocation |
0x50 | Auto AC Enable |
0x55 | Alternative Inrush and Powered Foldback Enable |
Changes to these registers after the DETE and CLE bits are set in Auto mode may result in undesired or non IEEE complaint operation.
The following registers may be configured or changed after turn on if changes to the default operation are desired as these values are internally set during power on based on the port configuration and resulting assigned PD class:
Register | Bits |
---|---|
0x1E-21 | 2-Pair Policing |
0x40 | 2x Foldback Enable |