SLVSF21D August 2019 – August 2020 TPS23882
PRODUCTION DATA
COMMAND = 19h with 1 Data Byte, Write Only
Push button register.
Used to initiate a channel(s) turn on or turn off in any mode except OFF mode.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POFF4 | POFF3 | POFF2 | POFF1 | PWON4 | PWON3 | PWON2 | PWON1 |
W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 |
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7–4 | POFF4–POFF1 | W | 0 | Channel power off bits |
3–0 | PWON4–PWON1 | W | 0 | Channel power on bits |
Writing a “1” at POFFn and PWONn on same Channel during the same write operation turns the Channel off.
The tOVLD, tLIM, tSTART and disconnect events have priority over the PWON command. During tOVLD, tLIM or tSTART, cool down cycle, any channel turn on using Power Enable command will be ignored and the Channel will be kept off.
PWONn in Diagnostic/Manual Mode:
If the PSE controller is configured in Diagnostic mode, writing a “1” at that PWONn bit location will immediately turn on the associated Channel.
PWONn in Semi Auto Mode:
While in Semi Auto mode, writing a “1” at a PWONn bit will attempt to turn on the associated Channel. If the detection or class results are invalid, the Channel is not turned on, and there will be no additional attempts to turn on the Channel until this push button is reasserted and the channel will resume its configured semi auto mode operation.
In Semi Auto mode, the Power Allocation (0x29h) value needs to be set prior to issuing a PWON command. Any changes to the Power Allocation value after a PWON command is given may be ignored.
CLEn | DETEn | Channel Operation | Result of PWONn Command |
---|---|---|---|
0 | 0 | Idle | Singular Turn On attempted with Full DET and CLS cycle |
0 | 1 | Cycling Detection Measurements only | Singular Turn On attempted with Full DET and CLS cycle |
1 | 0 | Idle | Singular Turn On attempted with Full DET and CLS cycle |
1 | 1 | Cycling Detection and Classification Measurements | Singular Turn On attempted after next (or current) DET and CLS cycle |
In semi auto mode with DETE and CLE set, as long as the PWONx command is received prior to the start of classification, the Channel will be powered immediately after classification is complete provided the classification result is valid and the power allocations settings (see register 0x29h) are sufficient to enable power on.
PWONn in Auto Mode:
In Auto mode with DETE or CLE set to 0, a PWONx command will initiate a singular detection and classification cycle and the port/channel will be powered immediately after classification is complete provided the classification result is valid and the power allocations settings (see register 0x29h) are sufficient to enable power on.
In Auto mode with DETE and CLE = 1, there is no need for a PWON command. The port/channel will automatically attempt to turn on after each detection and classification cycle.
In Auto mode, the Power Allocation (0x29h) value needs to be set prior to issuing a PWON command. Any changes to the Power Allocation value after a PWON command is given may be ignored.
CLEn | DETEn | Channel Operation | Result of PWONn Command |
---|---|---|---|
0 | 0 | Idle | Singular Turn On attempted with Full DET and CLS cycle |
0 | 1 | Cycling Detection Measurements only | Singular Turn On attempted with Full DET and CLS cycle |
1 | 0 | Idle | Singular Turn On attempted with Full DET and CLS cycle |
1 | 1 | Cycling Detection and Classification Measurements | NA - Channel will power automatically after a valid detection and classification |
PWOFFn in any Mode:
The channel is immediately disabled and the following registers are cleared:
Register | Bits to be Reset |
---|---|
0x04 | CLSCn and DETCn |
0x06 | DISFn and PCUTn |
0x08 | STRTn and ILIMn |
0x0C-0F | Requested Class and Detection |
0x10 | PGn and PEn |
0x14 | CLEn and DETEn |
0x1C | ACn |
0x1E-21 | 2P Policing set to 0xFFh |
0x24 | PFn |
0x30-3F | Channel Voltage and Current Measurements |
0x40 | 2xFBn |
0x44 - 47 | Detection Resistance Measurements |
0x4C-4F | Assigned Class and Previous Class |
0x51-54 | Autoclass Measurement |
It may take upwards of 5ms after PWOFFn command for all register values to be updated.
Only the bits associated with the channel/port ("n") with PWOFFn set will be cleared. Those bits associated with channels/ports remaining in operation will not be changed.