SLVSF21D August 2019 – August 2020 TPS23882
PRODUCTION DATA
COMMAND = 16h with 1 Data Byte, Read/Write
Bit Descriptions: These bits define the timing configuration for all four channels.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLIM | TSTART | TOVLD | TMPDO | ||||
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description | ||||
---|---|---|---|---|---|---|---|---|
7 –6 | TLIM | R/W | 0 | ILIM fault timing, which is
the output current limit time duration before channel turn off. When a 2xFBn bit in register 0x40 = 0, the tLIM used for the associated channel is always the nominal value (about 60 ms). This timer is active and increments to the settings defined below after expiration of the TSTART time window and when the channel is limiting its output current to ILIM. If the ILIM counter is allowed to reach the programmed time-out duration specified below, the channel will be powered off. The 1-second cool down timer is then started, and the channel can not be turned-on until the counter has reached completion. In other circumstances (ILIM time-out has not been reached), while the channel current is below ILIM, the same counter decrements at a rate 1/16th of the increment rate. The counter does not decrement below zero. The ILIM counter is also cleared in the event of a turn off due to a Power Enable or Reset command, a DC disconnect event or the OSS input. Note that in the event the TLIM setting is changed while this timer is already active for a channel, this timer is automatically reset then restarted with the new programmed time-out duration. Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically restarted if the detect enable bit is set. Also note that the cool down time count is immediately canceled with a reset command, or if the OFF or Manual mode is selected. If 2xFBn bit is asserted in register 0x40, then tLIM for associated channel is programmable with the following selection: |
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TLIM | Minimum tLIM (ms) | |||||||
0 | 0 | 58 | ||||||
0 | 1 | 15 | ||||||
1 | 0 | 10 | ||||||
1 | 1 | 6 | ||||||
5-4 | TSTART (or TINRUSH) |
R/W | 0 | START fault timing, which is
the maximum allowed overcurrent time during inrush. If at the end of TSTART period
the current is still limited to IInrush, the channel is powered off. This is followed by a 1-second cool down period, during which the channel can not be turned-on Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically restarted if the class and detect enable bits are set. Note that in the event the TSTART setting is changed while this timer is already active for a channel, this new setting is ignored and will be applied only next time the channel is turned ON. The selection is as following: |
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TSTART | Nominal tSTART (ms) | |||||||
0 | 0 | 60 | ||||||
0 | 1 | 30 | ||||||
1 | 0 | 120 | ||||||
1 | 1 | Reserved | ||||||
3–2 | TOVLD | R/W | 0 | PCUT fault timing, which is
the overcurrent time duration before turn off. This timer is active and increments
to the settings defined below after expiration of the TSTART time window and when
the current meets or exceeds PCUT, or when it is limited by the current
foldback. If the PCUT counter is allowed to reach the programmed time-out duration
specified below, the channel will be powered off. The 1-second cool down timer is
then started, and the channel can not be turned-on until the counter has reached
completion. In other circumstances (PCUT time-out has not been reached), while the current is below PCUT, the same counter decrements at a rate 1/16th of the increment rate. The counter does not decrement below zero. The PCUT counter is also cleared in the event of a turn off due to a Power Enable or Reset command, a DC disconnect event or the OSS input Note that in the event the TOVLD setting is changed while this timer is already active for a channel, this timer is automatically reset then restarted with the new programmed time-out duration. Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically restarted if the detect enable bit is set. Also note that the cool down time count is immediately canceled with a reset command, or if the OFF or Manual mode is selected. Note that if a DCUTn bit is high in the Power Priority/PCUT Disable register, the PCUT fault timing for the associated channel is still active. However, even though the channel will not be turned off when the tOVLD time expires, the PCUT fault bits will still be set. The selection is as following: |
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TOVLD | Nominal tOVLD (ms) | |||||||
0 | 0 | 60 | ||||||
0 | 1 | 30 | ||||||
1 | 0 | 120 | ||||||
1 | 1 | 240 | ||||||
1–0 | TMPDO | R/W | 0 | Disconnect delay, which is
the time to turn off a channel once there is a disconnect condition, and if the dc
disconnect detect method has been enabled. The TDIS counter is reset each time the current goes continuously higher than the disconnect threshold for nominally 15 ms. The counter does not decrement below zero. The selection is as following: |
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TMPDO | Nominal tMPDO (ms) | |||||||
0 | 0 | 360 | ||||||
0 | 1 | 90 | ||||||
1 | 0 | 180 | ||||||
1 | 1 | 180 | ||||||
The PGn and PEn bits (Power Status register) are cleared when there is a TLIM, TOVLD, TMPDO, or TSTART fault condition.
The settings for tLIM set the minimum timeout based on the IEEE compliance requirements.