SLUS599B June 2004 – October 2015 TPS2400
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VVIN | Input voltage | VIN | –0.3 | 110 | V |
VOUT | Output voltage | GATE (continuous) | –0.3 | 22 | V |
GATE (transient, < 10 µs, Duty Cycle < 0.1%) | –0.3 | 25 | |||
Continuous total power dissipation | See Thermal Information | ||||
TJ | Operating junction temperature | –40 | 125 | °C | |
TA | Operating free-air temperature | –40 | 85 | °C | |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2500 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Supply voltage at VIN | 3.1 | 6.8 | V | ||
Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS2400 | UNIT | |
---|---|---|---|
DBV (SOT-23) | |||
5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 219.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 126.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 51.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 15.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 50.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT | ||||||
II(VIN) | Input supply current, VIN | VI(VIN) = 3.1 V | 65 | 110 | µA | |
VI(VIN) = 5 V | 95 | 180 | ||||
VI(VIN) = 6.5 V | 135 | 220 | ||||
VI(VIN) = 100 V | 550 | 1000 | ||||
UVLO(upper) | Undervoltage lockout upper threshold | VI(VIN) rising | 2.9 | 3 | 3.1 | V |
UVLO(hyst) | Undervoltage lockout hysteresis | 85 | 100 | 115 | mV | |
OVP(upper) | Overvoltage protection upper threshold | VI(VIN) rising | 6.7 | 6.9 | 7.1 | V |
OVP(hyst) | Overvoltage protection hysteresis | 135 | 150 | 165 | mV | |
GATE DRIVE | ||||||
IOSOURCE(gate) | Gate sourcing current | VI(VIN) = 3.1 V, VO(gate) = 7 V | 3 | 10 | µA | |
VI(VIN) = 5 V, VO(gate) = 10 V | 3 | 10 | ||||
IOSINK(gate) | Gate sinking current(1) | VI(VIN) = 7.2 V, VO(gate) = 15 V | 350 | 485 | 600 | mA |
VOH(gate) | Gate output high voltage | VI(VIN) = 3.1 V, IOSOURCE(gate) = 1 µA | 10 | 12 | V | |
VI(VIN) = 5 V, IOSOURCE(gate) = 1.5 µA | 16 | 19 | ||||
VI(VIN) = 6.5 V, IOSOURCE(gate) = 1.5 µA | 16 | 20 | ||||
VOHMAX(gate) | Gate output high maximum voltage | IOSOURCE(gate) = 0 µA | 20 | V | ||
VOL(gate) | Gate output low voltage | VI(VIN) = 7.2 V, IOSINK(gate) = 50 mA | 1 | V | ||
TON(prop) | Gate turnon propogation delay, (50% VI(vin) to VO(gate) = 1 V, RLOAD = 10 MΩ |
VI(VIN) stepped from 0 V to 5 V, CLOAD = 1 nF | 0.1 | 0.6 | ms | |
CLOAD = 10 nF | 0.9 | 3 | ||||
TON(rise) | Gate turnon rise time, (VO(gate) = 1 V to 90%VO(gate), RLOAD = 10 MΩ) |
VI(VIN) stepped from 0 V to 5 V, CLOAD = 1 nF | 1.5 | 6 | ms | |
CLOAD = 10 nF | 15 | 55 | ||||
TOFF | Turnoff time, (50% VI(VIN) step to VO(GATE) = 6.9 V, RLOAD = 10 MΩ) | VI(VIN) stepped from 6 V to 8 V, CLOAD = 1 nF | 5 | 0.25 | µs | |
CLOAD = 10 nF | 5 | 0.5 |