Input and output capacitance improves the performance of the device; the actual capacitance should be optimized for the particular application. All protection circuits including the TPS2549-Q1 device have the potential for input voltage droop, overshoot, and output-voltage undershoot.

For all applications, TI recommends a 0.1-µF or greater ceramic bypass capacitor between IN and GND, placed as close as possible to the device for the local noise decoupling.

The TPS2549-Q1 device is used for 5-V power rail protection when a hot-short occurs on the output or when plugging in a capacitive load. Due to the limited response time of the upstream power supply, a large load transient can deplete the charge on the output capacitor of the power supply, causing a voltage droop. If the power supply is shared with other loads, ensure that voltage droop from current surges of the other loads do not force the TPS2549-Q1 device into UVLO. Increasing the upstream power supply output capacitor can reduce this droop. Shortening the connection impedance (resistance and inductance) between the TPS2549-Q1 device and the upstream power supply can also help reduce the voltage droop and overshoot on the TPS2549-Q1 input power bus.

Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input voltage in conjunction with input power-bus inductance and input capacitance when the IN terminal is in the high-impedance state (before turnon). Theoretically, the peak voltage is 2 times the applied voltage. The second cause is due to the abrupt reduction of output short-circuit current when the TPS2549-Q1 device turns off and energy stored in the input inductance drives the input voltage high. Applications with large input inductance (for example, connecting the evaluation board to the bench power supply through long cables) may require large input capacitance to prevent the voltage overshoot from exceeding the absolute maximum voltage of the device.

For output capacitance, consider the following three application situations.

The first, output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred and the TPS2549-Q1 has abruptly reduced OUT current. Energy stored in the inductance will drive the OUT voltage down and potentially negative as it discharges. Applications with large output inductance (such as from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. Second, for USB-port application, because the OUT pin is exposed to the air, the application must withstand ESD stress without damage. Because there is no internal IEC ESD cell as on DP_IN and DM_IN, using a low-ESR capacitance can make this pin robust. Third, when plugging in apacitive load such as the input capacitor of any portable device, having a large output capacitance can help reduce the peak current and up-stream power supply output voltage droop. So for TPS2549-Q1 output capacitance, recommended practice is typically adding two 47-µF ceramic capacitors.