SLVSC97B March   2014  – September 2020 TPS2556-Q1 , TPS2557-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Application
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Terminal Configuration and Functions
    1.     Terminal Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
      1.      16
        1.       Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Overcurrent Conditions
      2. 8.3.2 FAULT Response
      3. 8.3.3 Thermal Sense
    4. 8.4 Device Functional Modes
      1. 8.4.1 Undervoltage Lockout (UVLO)
      2. 8.4.2 Enable ( EN OR EN)
      3. 8.4.3 Auto-Retry Functionality
      4. 8.4.4 Two-Level Current-Limit Circuit
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application, Design for Current Limit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Determine Design Parameters
        2. 9.2.2.2 Programming the Current-Limit Threshold
        3. 9.2.2.3 Selecting Current-Limit Resistor 1
        4. 9.2.2.4 Selecting Current-Limit Resistor 2
        5. 9.2.2.5 Accounting for Resistor Tolerance
        6. 9.2.2.6 Power Dissipation and Junction Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 Enable ( EN OR EN)

The logic enable controls the power switch and device supply current. The supply current is reduced to less than 2 μA when a logic high is present on EN or when a logic low is present on EN. A logic low input on EN or a logic high input on EN enables the driver, control circuits, and power switch. The enable input is compatible with both TTL and CMOS logic levels.