SLVSGP9 October   2023 TPS25730

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
      1. 6.1.1 TPS25730D and TPS25730S - Absolute Maximum Ratings
      2. 6.1.2 TPS25730D - Absolute Maximum Ratings
      3. 6.1.3 TPS25730S - Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
      1. 6.3.1 TPS25730D - Recommended Operating Conditions
      2. 6.3.2 TPS25730S - Recommended Operating Conditions
    4. 6.4  Recommended Capacitance
    5. 6.5  Thermal Information
      1. 6.5.1 TPS25730D - Thermal Information
      2. 6.5.2 TPS25730S - Thermal Information
    6. 6.6  Power Supply Characteristics
    7. 6.7  Power Consumption
    8. 6.8  PPHV Power Switch Characteristics - TPS25730D
    9. 6.9  PP_EXT Power Switch Characteristics - TPS25730S
    10. 6.10 Power Path Supervisory
    11. 6.11 CC Cable Detection Parameters
    12. 6.12 CC PHY Parameters
    13. 6.13 Thermal Shutdown Characteristics
    14. 6.14 ADC Characteristics
    15. 6.15 Input/Output (I/O) Characteristics
    16. 6.16 I2C Requirements and Characteristics
    17. 6.17 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB-PD Physical Layer
        1. 8.3.1.1 USB-PD Encoding and Signaling
        2. 8.3.1.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.1.3 USB-PD BMC Transmitter
        4. 8.3.1.4 USB-PD BMC Receiver
        5. 8.3.1.5 Squelch Receiver
      2. 8.3.2  Power Management
        1. 8.3.2.1 Power-On And Supervisory Functions
        2. 8.3.2.2 VBUS LDO
      3. 8.3.3  Power Paths
        1. 8.3.3.1 TPS25730D Internal Sink Path
        2. 8.3.3.2 TPS25730S - External Sink Path Control PP_EXT
      4. 8.3.4  Cable Plug and Orientation Detection
      5. 8.3.5  Overvoltage Protection (CC1, CC2)
      6. 8.3.6  Default Behavior Configuration (ADCIN1, ADCIN2)
      7. 8.3.7  ADC
      8. 8.3.8  Digital Interfaces
      9. 8.3.9  Digital Core
      10. 8.3.10 I2C Interface
        1. 8.3.10.1 I2C Interface Description
          1. 8.3.10.1.1 I2C Clock Stretching
          2. 8.3.10.1.2 Unique Address Interface
          3. 8.3.10.1.3 Pin Strapping to Configure Default Behavior
      11. 8.3.11 Minimum Voltage Configuration
      12. 8.3.12 Maximum Voltage Configuration
      13. 8.3.13 Sink Current Configuration
      14. 8.3.14 Autonegotiate Sink Minimum Power
      15. 8.3.15 Extended Sink Capabilities Power Delivery Power
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power States
    5. 8.5 Schottky for Current Surge Protection
    6. 8.6 Thermal Shutdown
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Supported Sink Power Configurations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 3.3-V Power
        1. 9.3.1.1 VIN_3V3 Input Switch
      2. 9.3.2 1.5-V Power
      3. 9.3.3 Recommended Supply Load Capacitance
    4. 9.4 Layout
      1. 9.4.1 TPS25730D - Layout
        1. 9.4.1.1 Layout Guidelines
          1. 9.4.1.1.1 Top Placement and Bottom Component Placement and Layout
        2. 9.4.1.2 Layout Example
        3. 9.4.1.3 Component Placement
        4. 9.4.1.4 Routing VBUS, VIN_3V3, LDO_3V3, LDO_1V5
        5. 9.4.1.5 Routing CC and GPIO
      2. 9.4.2 TPS25730S - Layout
        1. 9.4.2.1 Layout Guidelines
          1. 9.4.2.1.1 Top Placement and Bottom Component Placement and Layout
        2. 9.4.2.2 Layout Example
        3. 9.4.2.3 Component Placement
        4. 9.4.2.4 Routing VBUS, PPHV, VIN_3V3, LDO_3V3, LDO_1V5
        5. 9.4.2.5 Routing CC and GPIO
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.16 I2C Requirements and Characteristics

994

Operating under these conditions unless otherwise noted: , 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SDA and SCL Common Characteristics Target)
VIL Input low signal VLDO_3V3=3.3V, 0.54 V
VIH Input high signal VLDO_3V3=3.3V,  1.3 V
VHYS Input hysteresis VLDO_3V3=3.3V 0.165 V
VOL Output low voltage IOL=3 mA 0.36 V
ILEAK Input leakage current Voltage on pin = VLDO_3V3 –3 3 µA
IOL Max output low current VOL=0.4 V 15 mA
IOL Max output low current VOL=0.6 V 20 mA
tf Fall time from 0.7*VDD to 0.3*VDD VDD = 1.8V, 10 pF ≤ Cb ≤ 400 pF 12 80 ns
tf Fall time from 0.7*VDD to 0.3*VDD VDD = 3.3V, 10 pF ≤ Cb ≤ 400 pF 12 150 ns
tSP I2C pulse width suppressed 50 ns
CI pin capacitance (internal) 10 pF
Cb Capacitive load for each bus line (external) 400 pF
SDA and SCL Standard Mode Characteristics (Target)
fSCLS Clock frequency for target VDD = 1.8V or 3.3V 100 kHz
tVD;DAT Valid data time Transmitting Data, VDD = 1.8V or 3.3V, SCL low to SDA output valid 3.45 µs
tVD;ACK Valid data time of ACK condition Transmitting Data, VDD = 1.8V or 3.3V, ACK signal from SCL low to SDA (out) low 3.45 µs
SDA and SCL Fast Mode Characteristics (Target)
fSCLS Clock frequency for target VDD = 1.8V or 3.3V 100 400 kHz
tVD;DAT Valid data time Transmitting data, VDD = 1.8V, SCL
low to SDA output valid		 0.9 µs
tVD;ACK Valid data time of ACK condition Transmitting data, VDD = 1.8V or 3.3V, ACK
signal from SCL low to SDA (out) low		 0.9 µs
fSCLS Clock frequency for Fast Mode Plus VDD = 1.8V or 3.3V 400   800 kHz
tVD;DAT Valid data time Transmitting data, VDD = 1.8V or 3.3V, SCL
low to SDA output valid		 0.55 µs
tVD;ACK Valid data time of ACK condition Transmitting data, VDD = 1.8V or 3.3V, ACK
signal from SCL low to SDA (out) low		 0.55 µs