SLVSDR6C June 2017 – March 2018 TPS25740B
PRODUCTION DATA.
R(FBL1), R(FBL2), and R(FBL3) provide a means to change the power supply output voltage when switched in by the CTL1, CTL2, and CTL3 open drain outputs, respectively. When CTLx is driven low it will place R(FBLx) in parallel with R(FBL).
R(FBL2) is calculated using Equation 5. In this example, VOUT9 is 9 V, VOUT15 is 15 V, and VOUT20 is 20 V. VOUT is the default output voltage (5 V) for the regulator and is set by R(FBU), R(FBL) and error amplifier VREF.
R(FBL1) is calculated using Equation 6 after a standard 1% value for R(FBL2) is chosen.
R(FBLx) resistors should be large enough so that the corresponding CTLx sinking current is minimized (< 1 mA). The sinking current for CTLx is VREF / R(FBLx).