SLVSDJ5 Data sheet | TI.com

SLVSDJ5D August 2016 – January 2018 TPS25741 , TPS25741A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RSM|32
- MPQF195B

Thermal pad, mechanical data (Package|Pins)

RSM|32
- QFND112H

Orderable Information

9.2.1.2.3 Configurable Components

C_RX: Choose C_RX between 200 pF and 600 pF. A 470 pF, 50 V, ±5% COG/NPO ceramic is recommended for both CC1 and CC2 pins.

Q_1A/Q_1B: For a 3-A application, an N-Channel MOSFET with R_DS(on) in the 10 mΩ range is sufficient. BV_DSS should be rated for 30 V for applications delivering 20 V, and 25 V for 12 V applications. For this application, the TI CSD17579Q3A (SLPS527) NexFET™ is suitable.
D_Q1B: During the dead time between Q1B open and Q2 closed, 5V current is sourced onto VBUS through the body diode of Q1B with a small voltage drop. To reduce the voltage drop, an external Schottky can be added in parallel with Q1B.
Q_2A/Q_2B: For a 3-A application, an P-Channel MOSFET with R_DS(on) in the 10 mΩ range is sufficient. BV_DSS should be rated for 30 V for applications delivering 20 V and 20 V for 12 V applications. For this application, the TI CSD25404Q3 (SLPS570) NexFET™ is suitable.
R_S: TPS25741 or TPS25741A OCP set point thresholds are targeted towards a 5 mΩ, ±1% sense resistor. Power dissipation for R_S at 3 A load is approximately 45 mW.
R_DSCG: The minimum value of R_DSCG is chosen based on the application V_BUS(max) and I_DSCGT. For V_BUS(max) = 12 V and I_DSCGT= 350 mA, R_DSCG(min) = 34.3 Ω. The size of the external resistor can then be chosen based on the capacitive load that needs to be discharged and the maximum allowed discharge time of 265 ms. Typically, a 120 Ω, 0.5 W resistor provides suitable performance.
R_F/C_F: Provide filtering of both ripple and transients. For this example, RF is a 24 Ω, 5% resistor and CF is a 0.33 μF, ceramic capacitor.

C_PDIN: The requirement for C_PDIN is 10 µF maximum. A 6.8 µF, 25 V, ±10% X5R or X7R ceramic capacitor is suitable for most applications.

D_VBUS: D_VBUS provides reverse transient protection during large transient conditions when inductive loads are present. A Schottky diode with a V_RRM rating of 30 V in a SMA package such as the B340A-13-F provides suitable reverse voltage clamping performance.

C_SLEW: To achieve a slew rate from zero to 5 V of less than 30 mV/µs using the typical GDNG current of 20 µA then C_SLEW (nF) > 20 µA/30 mV/µs = 0.67 nF be used. Choosing C_SLEW = 10 nF yields a ramp rate of 2 mV/µs.

R_FBL1/R_FBL2: Not used

C_SLU/C_SLL: Not used

R_PPU: R_PPU is the Q2 gate drive pullup resistor. The TPS25741 applies a sink current of 40 µA typical to turn on Q2 and R_PPU should be large enough to fully enhance Q2 but not too large as it also discharges C_SLP during turn off. The CSD25404Q3 lists an acceptable R_DS(on) with V_GS = -4.5V and I_D = -10A. Using I_GMV(min) = 34 µA and V_GS = -4.5V yields R _PPU = 132kΩ. Use a standard 1% resistor = 133kΩ resistor for R_PPU.

C_SLP: C_SLP provides slew rate and inrush current limiting from the 12 V supply during VBUS transition from 5 V to 12 V. While the sink is attached, there could be as much as 110 µF on VBUS. The slew time must be > 233 µs and the inrush current must be < 3.85 A (V_ITRIP(min)/RS). For this design, target an inrush current of 2 A during 5 V to 12 V slew. The charge rate across C_SLP will be the same as for the 110 µF load capacitor such that I_LOAD/C_LOAD = I_CSLP/C_SLP. Using the CSD25404Q3 Gate Charge curve, a plateau threshold voltage of V_PTH ~ 1.8 V can be used to calculate C_SLP with the equations below.

TPS25741 TPS25741A eq12_slvsdj5.gif

Equation 14. C_LOAD = 110 µF, I_GDPG = 40 µA, V_PTH = 1.8V, R_PPU = 133 kΩ, I_LOAD = 2 A

TPS25741 TPS25741A eq13_slvsdj5.gif

Choose C_SLP = 1.5 nF

TPS25741 TPS25741A eq14_slvsdj5.gif

C_PPU: C_PPU contributes a small Q2 turn on delay just prior to the 5 V to 12 V transition, but the primary function is to inhibit Q2 output turn on during ramp up of the 12 V power supply. When the 12 V power supply is OFF C_SLP will be discharged. As the 12 V power supply ramps up, the common sources of Q2 will rise and C_SLP will be charged through R_PPU. C_PPU is required to prevent Q2 V_GS from exceeding the turn on threshold and prematurely charging VBUS for the case where the 12V bus ramps up quickly. C_PPU and C_SLP form a capacitive divider network with V_GS(th) ≈ 12 V x C_SLP / (C_SLP + C_PPU). Choose C_PPU ≈ (12 V/V_GS(th) –1) x C_SLP. For this example, V_GS(th) = 0.9 V and C_PPU = 18 nF. If the 12 V power supply is enabled while the 5 V supply is on then C_PPU can be smaller set by the voltage difference between the 12 V and 5 V supply. Always validate the final design on the test bench.

For faster fault turn off, Q3 can be connected as shown in Figure 51 and triggered using the GDNG pin. Q3 must have a ±20V V_GS(max) rating for 20 V muxing applications.

TPS25741 TPS25741A Fast_turnoff_cir_slvsdj5.gif

Figure 51. Fast Turnoff Circuit

Power Supply ON/OFF Considerations: For applications that can disable one or both of the power supplies, additional considerations apply. Refer to the TPS25741EVM-802 User Guide (refer to Documentation Support). for more information.