SLVSDJ5D August   2016  – January 2018 TPS25741 , TPS25741A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Implementations in DFP Host Ports
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 VBUS Capacitance
      2. 8.1.2 USB Data Communications
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB Type-C CC Logic (CC1, CC2)
      2. 8.3.2  9.3.2 VCONN Supply (VCONN, CC1, CC2)
      3. 8.3.3  USB Power Delivery BMC Transmission (CC1, CC2, VTX)
      4. 8.3.4  USB Power Delivery BMC Reception (CC1, CC2)
      5. 8.3.5  Discharging (DSCG, VPWR)
        1. 8.3.5.1 Discharging after a Fault (VPWR)
      6. 8.3.6  Configuring Voltage Capabilities (HIPWR, EN9V, EN12V)
      7. 8.3.7  Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
      8. 8.3.8  Gate Drivers
        1. 8.3.8.1 GDNG, GDNS
        2. 8.3.8.2 G5V
        3. 8.3.8.3 GDPG
      9. 8.3.9  Fault Monitoring and Protection
        1. 8.3.9.1 Over/Under Voltage (VBUS)
        2. 8.3.9.2 Over-Current Protection (ISNS, VBUS)
        3. 8.3.9.3 System Fault Input (GD, VPWR)
      10. 8.3.10 Voltage Control (CTL1, CTL2)
      11. 8.3.11 Sink Attachment Indicator (UFP, DVDD)
      12. 8.3.12 Accessory Attachment Indicator (AUDIO, DEBUG)
      13. 8.3.13 Plug Polarity Indication (POL)
      14. 8.3.14 Power Supplies (VAUX, VDD, VPWR, DVDD)
      15. 8.3.15 Grounds (AGND, GND)
      16. 8.3.16 Output Power Supply (DVDD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Checking VBUS at Start Up
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 System-Level ESD Protection
      2. 9.1.2 Use of GD Internal Clamp
      3. 9.1.3 Resistor Divider on GD for Programmable Start Up
      4. 9.1.4 Selection of the CTL1 and CTL2 Resistors (RFBL1 and RFBL2)
      5. 9.1.5 Voltage Transition Requirements
      6. 9.1.6 VBUS Slew Control using GDNG CSLEW
      7. 9.1.7 Tuning OCP Using RF and CF
    2. 9.2 Typical Applications
      1. 9.2.1 A/C Multiplexing Power Source
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power Pin Bypass Capacitors
          2. 9.2.1.2.2 Non-Configurable Components
          3. 9.2.1.2.3 Configurable Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 D/C Power Source
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Power Pin Bypass Capacitors
          2. 9.2.2.2.2 Non-Configurable Components
          3. 9.2.2.2.3 Configurable Components
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 A/C Power Source (Wall Adapter)
      2. 9.3.2 Dual-Port Power Managed A/C Power Source (Wall Adapter)
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VCONN
    3. 10.3 VPWR
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Port Current Kelvin Sensing
      2. 11.1.2 Power Pin Bypass Capacitors
      3. 11.1.3 Supporting Components
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RSM Package
32-Pin VQFN
Top View

Pin Functions

PINTYPEDESCRIPTION
NAMENUMBER
AGND 23 — Analog ground is associated with monitoring and power conditioning circuits. Connect to GND and PAD.
AUDIO 28 O Low when an audio accessory is present, high-z otherwise.
CC1 2 I/O Multifunction configuration channel interface pin to USB Type-C. Functions include connector polarity, end-device connection detect, current capabilities, and Power Delivery communication.
CC2 4 I/O Multifunction configuration channel interface pin to USB Type-C. Functions include connector polarity, end-device connection detect, current capabilities, and Power Delivery communication.
CTL1 7 O Digital output pin used to control an external voltage regulator.
CTL2 8 O Digital output pin used to control an external voltage regulator.
DEBUG 15 O Low when a debug accessory is present, high-z otherwise.
DSCG 31 O Discharge is an open-drain output that discharges the system VBUS line through an external resistor.
DVDD 18 O Internally regulated 1.85 V rail for external use up to 35 mA. Connect this pin to GND via the recommended bypass capacitor.
EN9V/EN12V 10 I For TPS25741:
If it is pulled high, then the 12 V PDO may be transmitted. If it is pulled low, the 12-V PDO will not be advertised.
For TPS25741A:
If it is pulled high, then the 9 V PDO may be transmitted. If it is pulled low, the 9-V PDO will not be advertised.
GDPG 27 O High-voltage open drain gate driver which may be used to drive PMOS power switches.
G5V 32 O Analog gate drive output for an external NMOS power switch.
GD 20 I Master enable for the GDNG/GDNS gate driver. The system can drive this low to force the power path switch off.
GDNG 29 O High-voltage open drain gate driver which may be used to drive NMOS power switches. Connect to the gate terminal.
GDNS 30 O High-voltage open drain gate driver which may be used to drive NMOS power switches. Connect to the source terminal.
GND 5 — Power ground is associated with power management and gate driver circuits. Connect to AGND and PAD.
HIPWR 6 I Four-state input pin used to configure the voltages and currents that will be advertised. It may be connected directly to GND or DVDD, or it may be connected to GND or DVDD via a resistance RSEL.
ISNS 24 I The ISNS input is used to monitor a VBUS-referenced sense resistor for over-current events.
PCTRL 19 I Input pin used to control the power that will be advertised. It may be pulled high or low dynamically.
POL 9 O Low when a UFP is connected on CC2, high-z otherwise.
PSEL 16 I A four-state input used for selecting the maximum power that can be provided. It may be connected directly to GND or DVDD, or it may be connected to GND or DVDD via a resistance RSEL
UFP 14 O Digital output pin used to indicate that either CC1 or CC2 (but not both) is pulled down by a USB Type-C Sink.
VAUX 21 O Internally regulated rail for use by the power management circuits. Connect this pin to GND via the recommended bypass capacitor.
VBUS 26 I The voltage monitor for the VBUS line. The USB connector VBUS line is the high-side power conductor.
VCONN 3 I The voltage applied to this pin will be internally current limited and routed through the TPS25741 to the CCx pin that is not connected to the CC wire in the USB cable once the UFP pin is pulled low. Connect this pin to GND via the recommended bypass capacitor.
VDD 22 I Optional input supply.
VIO 17 I Connect VIO to the DVDD pin.
VPWR 25 I Connect to an external voltage as a source of bias power. If VDD is supplied, this supply is optional while is UFP high.
VTX 1 O Bypass pin for transmit driver supply. Use a 0.1-µF ceramic capacitor.
N/C 11 Connect to GND.
N/C 12 Connect to GND.
N/C 13 Connect to GND.
THERMAL PAD Connect PAD to GND / AGND plane.