SLVSDJ5D August   2016  – January 2018 TPS25741 , TPS25741A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Implementations in DFP Host Ports
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 VBUS Capacitance
      2. 8.1.2 USB Data Communications
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB Type-C CC Logic (CC1, CC2)
      2. 8.3.2  9.3.2 VCONN Supply (VCONN, CC1, CC2)
      3. 8.3.3  USB Power Delivery BMC Transmission (CC1, CC2, VTX)
      4. 8.3.4  USB Power Delivery BMC Reception (CC1, CC2)
      5. 8.3.5  Discharging (DSCG, VPWR)
        1. 8.3.5.1 Discharging after a Fault (VPWR)
      6. 8.3.6  Configuring Voltage Capabilities (HIPWR, EN9V, EN12V)
      7. 8.3.7  Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
      8. 8.3.8  Gate Drivers
        1. 8.3.8.1 GDNG, GDNS
        2. 8.3.8.2 G5V
        3. 8.3.8.3 GDPG
      9. 8.3.9  Fault Monitoring and Protection
        1. 8.3.9.1 Over/Under Voltage (VBUS)
        2. 8.3.9.2 Over-Current Protection (ISNS, VBUS)
        3. 8.3.9.3 System Fault Input (GD, VPWR)
      10. 8.3.10 Voltage Control (CTL1, CTL2)
      11. 8.3.11 Sink Attachment Indicator (UFP, DVDD)
      12. 8.3.12 Accessory Attachment Indicator (AUDIO, DEBUG)
      13. 8.3.13 Plug Polarity Indication (POL)
      14. 8.3.14 Power Supplies (VAUX, VDD, VPWR, DVDD)
      15. 8.3.15 Grounds (AGND, GND)
      16. 8.3.16 Output Power Supply (DVDD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Checking VBUS at Start Up
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 System-Level ESD Protection
      2. 9.1.2 Use of GD Internal Clamp
      3. 9.1.3 Resistor Divider on GD for Programmable Start Up
      4. 9.1.4 Selection of the CTL1 and CTL2 Resistors (RFBL1 and RFBL2)
      5. 9.1.5 Voltage Transition Requirements
      6. 9.1.6 VBUS Slew Control using GDNG CSLEW
      7. 9.1.7 Tuning OCP Using RF and CF
    2. 9.2 Typical Applications
      1. 9.2.1 A/C Multiplexing Power Source
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power Pin Bypass Capacitors
          2. 9.2.1.2.2 Non-Configurable Components
          3. 9.2.1.2.3 Configurable Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 D/C Power Source
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Power Pin Bypass Capacitors
          2. 9.2.2.2.2 Non-Configurable Components
          3. 9.2.2.2.3 Configurable Components
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 A/C Power Source (Wall Adapter)
      2. 9.3.2 Dual-Port Power Managed A/C Power Source (Wall Adapter)
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VCONN
    3. 10.3 VPWR
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Port Current Kelvin Sensing
      2. 11.1.2 Power Pin Bypass Capacitors
      3. 11.1.3 Supporting Components
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Switching Characteristics

Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ TJ ≤ 125°C; 3.0 V ≤ VDD ≤ 5.5 V, 4.65 V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND, EN9V = GND; EN12V = GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tVP Delay from enabling external NFET until under-voltage and OCP protection are enabled VBUS = GND 190 ms
tSTL Source settling time, time from CTL1 and CTL2 being changed until a PS_RDY USB Power Delivery message is transmitted to inform the sink is may draw full current per USB Power Delivery in Documentation Support. 260 ms
tSR Time that VBUS is held low after a hard reset. This is tSrcRecover in USB Power Delivery in Documentation Support. TJ > TJ1 765 ms
tHR Time after hard reset is transmitted until GDNG is disabled. This is tPSHardReset in USB Power Delivery in Documentation Support. 30 ms
tCCDeb Time until UFP or AUDIO or DEBUG is pulled low after an attachment, this is the USB Type-C required debounce time for attachment detection called tCCDebounce [1]. 185 ms
tST Delay after sink request is accepted until CTL1 and/or CTL2 is changed. This is called tSnkTransition in USB Power Delivery in Documentation Support. 30 ms
tFLT The time in between hard reset transmissions in the presence of a persistent supply fault. GD = GND or VPWR = GND, sink attached 1395 ms
tSH The time in between retries (hard reset transmissions) in the presence of a persistent VBUS short. VBUS = GND, sink attached 985 ms
tON The time from UFP being pulled low until a hard reset is transmitted. Designed to be greater than tSrcTurnOn in USB Power Delivery in Documentation Support. GD = 0 V or VPWR = 0 V 600 ms
Retry interval if USB Power Delivery sink stops communicating without being removed or if sink does not communicate after a fault condition. Time GDNG remains enabled before a hard reset is transmitted. This is the tNoResponse time in USB Power Delivery in Documentation Support. Sink attached 4.8 s
tDVDD Delay before DVDD is driven high After sink attached 5 ms
tGDoff Turnoff delay, time until VGDNG is below 10% of its initial value after the GD pin is low. VGD: 5 V → 0 V in < 0.5 µs. 5 µs
tFOVP Response time when VBUS exceeds the fast-OVP threshold VBUS ↑ to GDNG OFF
(VGDNG below 10% its initial value)		 30 µs
OCP large signal response time 5 A enabled, VISNS – VVBUS: 0 V → 42 mV measured to GDNG transition start. 30 µs
Time until discharge is stopped after TJ1 is exceeded. 0 V ≤ VDSCG ≤ 25 V 10 µs
Digital output fall time VPULLUP = 1.8 V, CLoad = 10 pF,
RPULLUP = 10 kΩ, V(CTLx) or
VUFP : 70% VPULLUP → 30% VPULLUP		 20 300 ns
tVCON VCONN turn-on time Measured from when UFP is pulled low until VCONN FET is enabled. 2 ms
VBUS turn-on time Measured from when UFP is pulled low until GDNG begins sourcing its full current 2 ms
TPS25741 TPS25741A timing1_slvsdj5.gifFigure 1. Timing Diagram for tVP, tST, and tSTL, After Sink Attachment. VSOVP and VSUVP are Disabled Around Voltage Transitions
TPS25741 TPS25741A timing2_slvsdj5.gifFigure 2. Timing Diagram for tHR and tSR, After Sink Attachment with TJ > TJ1
TPS25741 TPS25741A timing3_slvsdj5.gifFigure 3. Timing Diagram for tCcDeb and tCD, Under Persistent Fault Condition
TPS25741 TPS25741A timing4_slvsdj5.gifFigure 4. Timing Diagram for tSH and tVP, with VBUS Shorted to Ground
TPS25741 TPS25741A timing6_slvsdj5.gifFigure 5. Timing Diagram for tON
TPS25741 TPS25741A timing7_slvsdj5.gifFigure 6. Timing Diagram for GDPG, G5V, and GDNG with Fast-Shutdown Fault