SLVSDJ5D August   2016  – January 2018 TPS25741 , TPS25741A

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Implementations in DFP Host Ports
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 VBUS Capacitance
      2. 8.1.2 USB Data Communications
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  USB Type-C CC Logic (CC1, CC2)
      2. 8.3.2  9.3.2 VCONN Supply (VCONN, CC1, CC2)
      3. 8.3.3  USB Power Delivery BMC Transmission (CC1, CC2, VTX)
      4. 8.3.4  USB Power Delivery BMC Reception (CC1, CC2)
      5. 8.3.5  Discharging (DSCG, VPWR)
        1. 8.3.5.1 Discharging after a Fault (VPWR)
      6. 8.3.6  Configuring Voltage Capabilities (HIPWR, EN9V, EN12V)
      7. 8.3.7  Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
      8. 8.3.8  Gate Drivers
        1. 8.3.8.1 GDNG, GDNS
        2. 8.3.8.2 G5V
        3. 8.3.8.3 GDPG
      9. 8.3.9  Fault Monitoring and Protection
        1. 8.3.9.1 Over/Under Voltage (VBUS)
        2. 8.3.9.2 Over-Current Protection (ISNS, VBUS)
        3. 8.3.9.3 System Fault Input (GD, VPWR)
      10. 8.3.10 Voltage Control (CTL1, CTL2)
      11. 8.3.11 Sink Attachment Indicator (UFP, DVDD)
      12. 8.3.12 Accessory Attachment Indicator (AUDIO, DEBUG)
      13. 8.3.13 Plug Polarity Indication (POL)
      14. 8.3.14 Power Supplies (VAUX, VDD, VPWR, DVDD)
      15. 8.3.15 Grounds (AGND, GND)
      16. 8.3.16 Output Power Supply (DVDD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Checking VBUS at Start Up
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 System-Level ESD Protection
      2. 9.1.2 Use of GD Internal Clamp
      3. 9.1.3 Resistor Divider on GD for Programmable Start Up
      4. 9.1.4 Selection of the CTL1 and CTL2 Resistors (RFBL1 and RFBL2)
      5. 9.1.5 Voltage Transition Requirements
      6. 9.1.6 VBUS Slew Control using GDNG CSLEW
      7. 9.1.7 Tuning OCP Using RF and CF
    2. 9.2 Typical Applications
      1. 9.2.1 A/C Multiplexing Power Source
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power Pin Bypass Capacitors
          2. 9.2.1.2.2 Non-Configurable Components
          3. 9.2.1.2.3 Configurable Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 D/C Power Source
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Power Pin Bypass Capacitors
          2. 9.2.2.2.2 Non-Configurable Components
          3. 9.2.2.2.3 Configurable Components
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 A/C Power Source (Wall Adapter)
      2. 9.3.2 Dual-Port Power Managed A/C Power Source (Wall Adapter)
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VCONN
    3. 10.3 VPWR
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Port Current Kelvin Sensing
      2. 11.1.2 Power Pin Bypass Capacitors
      3. 11.1.3 Supporting Components
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.5 Voltage Transition Requirements

During VBUS voltage transitions, the slew rate (vSrcSlewPos in USB in Documentation Support) must be kept below 30 mV/µs in all portions of the waveform, settle (tSrcSettle) in less than 275 ms, and be ready (tSrcReady in USB in Documentation Support) in less than 285 ms. For most power supplies, these requirements are met naturally without any special circuitry but in some cases, the voltage transition ramp rate must be slowed in order to meet the slew rate requirement.

The requirements for linear voltage transitions are shown in Table 7. In all cases, the minimum slew time is below 1 ms.

Table 7. Minimum Slew-Rate Requirements

VOLTAGE TRANSITION 5 V ↔ 12 V 5 V ↔ 20 V 12 V ↔ 20 V 5 V ↔ 9 V 5 V ↔ 15 V 9 V ↔ 15 V
Minimum Slew Time 233 µs 500 µs 267 µs 133 µs 333 µs 200 µs

When transition slew control is required, the interaction of the slew mechanism and dc/dc converter loop response must be considered. A simple R-C filter between the device CTL pins and converter feedback node may lead to instability under some conditions. Figure 46 shows a method which manages the slew control without adding capacitance to the converter feedback node.

TPS25741 TPS25741A Slew_rate1_slvsdj5.gifFigure 46. Slew-Rate Control Example Number 1

When VOUT = 5 V, both CTL1 and CTL2 are in a high impedance state. When a 5 V to 12 V transition is requested, CTL2 goes low and turns off QCTL2. QSL2 gate starts to rise towards VCC at a rate determined by RSL2A + RSL2B and CSL2. QSL2 gate continues to rise, until QSL2 is fully enhanced placing RFBL2 in parallel with RFBL. In similar fashion when CTL1 goes low, QCTL1 turns off allowing RFBL1 to slew in parallel with RFBL2 and RFBL.

The slewing resistors and capacitor can be chosen using the following equations. VT is the VGS threshold voltage of QSL1 and QSL2. VREF is the feedback regulator reference voltage. Choose the slewing resistance in the 100 kΩ range to reduce the loading on the bias voltage source (VCC) and then calculate CSL. The falling transitions are shorter than the rising transitions in this topology.

Falling transitions:

  • 20 V to 12 V

Equation 6. TPS25741 TPS25741A eq5_slvsdj5.gif

  • 12 V to 5 V

Equation 7. TPS25741 TPS25741A eq6_slvsdj5.gif

Rising transitions:

  • 5 V to 12 V

Equation 8. TPS25741 TPS25741A eq7_slvsdj5.gif

  • 12 V to 20 V

Equation 9. TPS25741 TPS25741A eq8_slvsdj5.gif

Some converter regulators can tolerate a balance of capacitance on the feedback node without affecting loop stability. The LM5175 has been tested using Figure 47 to combine VOUT slewing with a minimal amount of extra circuitry.

TPS25741 TPS25741A Slew_rate3_slvsdj5.gifFigure 47. Slew-Rate Control Example Number 2

When a higher voltage is requested from TPS25741, CTL1 or CTL2 goes low changing the sensed voltage at the FB pin. The LM5175 compensates by increasing VOUT. As VOUT increases, CSLU is charged at a rate proportional to RFBU. Three time constants yield a voltage change of approximately 95% and can be used to calculate the desired slew time. CSLU can be calculated using Equation 10 and Equation 11.

Equation 10. TPS25741 TPS25741A eq9_slvsdj5.gif
Equation 11. TPS25741 TPS25741A eq10_slvsdj5.gif

In order to minimize loop stability effects, a capacitor CSLL in parallel with RFBL is required. The ratio of CSLU/CSLL should be chosen to match the ratio of RFBL/RFBU. Choose CSLL according to Equation 12.

Equation 12. TPS25741 TPS25741A eq11_slvsdj5.gif

All slew rate control methods should be verified on the bench to ensure that the slew rate requirements are being met when the external VBUS capacitance is between 1 μF and 100 μF.