SLVSGL9B December   2022  – October 2024 TPS25762-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Recommended Components
    5. 6.5  Thermal Information
    6. 6.6  Buck-Boost Regulator
    7. 6.7  CC Cable Detection Parameters
    8. 6.8  CC VCONN Parameters
    9. 6.9  CC PHY Parameters
    10. 6.10 Thermal Shutdown Characteristics
    11. 6.11 Oscillator Characteristics
    12. 6.12 ADC Characteristics
    13. 6.13 TVSP Parameters
    14. 6.14 Input/Output (I/O) Characteristics
    15. 6.15 BC1.2 Characteristics
    16. 6.16 I2C Requirements and Characteristics
    17. 6.17 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power Management and Supervisory Circuitry
        1. 8.3.1.1 VIN UVLO and Enable/UVLO
        2. 8.3.1.2 Internal LDO Regulators
      2. 8.3.2  TVSP Device Configuration and ESD Protection
      3. 8.3.3  Buck-Boost Regulator
        1. 8.3.3.1  Buck-Boost Regulator Operation
        2. 8.3.3.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 8.3.3.3  VIN Supply and VIN Over-Voltage Protection
        4. 8.3.3.4  Feedback Paths and Error Amplifiers
        5. 8.3.3.5  Transconductors and Compensation
        6. 8.3.3.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 8.3.3.7  VBUS Overvoltage Protection
        8. 8.3.3.8  VBUS Undervoltage Protection
        9. 8.3.3.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 8.3.3.10 Buck-Boost Peak Current Limits
      4. 8.3.4  USB-PD Physical Layer
        1. 8.3.4.1 USB-PD Encoding and Signaling
        2. 8.3.4.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.4.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.4.4 USB-PD BMC Transmitter
        5. 8.3.4.5 USB-PD BMC Receiver
        6. 8.3.4.6 Squelch Receiver
      5. 8.3.5  VCONN
      6. 8.3.6  Cable Plug and Orientation Detection
        1. 8.3.6.1 Configured as a Source
        2. 8.3.6.2 Configured as a Sink
        3. 8.3.6.3 Overvoltage Protection (Px_CC1, Px_CC2)
      7. 8.3.7  ADC
        1. 8.3.7.1 ADC Divider Ratios
      8. 8.3.8  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      9. 8.3.9  USB2.0 Low-Speed Endpoint
      10. 8.3.10 Digital Interfaces
        1. 8.3.10.1 General GPIO
        2. 8.3.10.2 I2C Buffer
      11. 8.3.11 I2C Interface
        1. 8.3.11.1 I2C Interface Description
        2. 8.3.11.2 I2C Clock Stretching
        3. 8.3.11.3 I2C Address Setting
        4. 8.3.11.4 Unique Address Interface
        5. 8.3.11.5 I2C Pullup Resistor Calculation
      12. 8.3.12 Digital Core
        1. 8.3.12.1 Device Memory
        2. 8.3.12.2 Core Microprocessor
      13. 8.3.13 NTC Input
      14. 8.3.14 Thermal Sensors and Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application GUI Selections
        2. 9.2.2.2 EEPROM Selection
        3. 9.2.2.3 EN/UVLO
        4. 9.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 9.2.2.5 Inductor Currents
        6. 9.2.2.6 Output Capacitor
        7. 9.2.2.7 Input Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     103

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RQL|29
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1: –40°C to +125°C ambient operating temperature range
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C2b
    • Enhanced connector pin ESD protection
  • USB power delivery (PD) controller with programmable power supply (PPS) support
    • Wide VIN: 5.5V to 18V (40V maximum)
    • Integrated buck-boost with 4 power switches supporting up to 65W USB PD output power
    • VBUS output: 3.3–21V with ±20mV step size
    • IBUS output: 0–3A with ±50mA current limit step size
    • VBUS short circuit to VBAT and GND protection
    • VBUS cable droop compensation
    • MFi overcurrent protection
    • Switching frequency: 300, 400, 450kHz
    • DC/DC sync in/out with dithering
  • USB port configuration options
    • 1 USB-PD port (TPS25762-Q1)
    • 1 USB-PD port with DisplayPort™ over USB-C™ (DP alternate mode) (TPS25763-Q1)
    • 2 USB-PD ports (TPS25772-Q1)
  • Compliant to USB
    • USB Type-C® power delivery Rev 3.1
      • TPS25762-Q1: USB–IF certification with PPS, TID: 9509
      • TPS25772-Q1: USB–IF certification with PPS, TID: 9161
      • CC logic, VCONN source and discharge
      • USB cable polarity detection
    • Battery charging specification v1.2 (BC1.2)
      • DCP: dedicated charging port
  • Legacy fast charging
    • 2.7V divider-3 mode
    • 1.2V divider mode
    • high voltage DCP Protocol
  • Microcontroller core allows
  • Short to VBUS and VBAT protection
    • VBUS
    • Px_ DP and Px_DM
    • Px_CC1 and Px_CC2
  • HotRod™ QFN package with wettable flank