SLVSGO0 October   2024 TPS25763-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Recommended Components
    5. 6.5  Thermal Information
    6. 6.6  Buck-Boost Regulator
    7. 6.7  CC Cable Detection Parameters
    8. 6.8  CC VCONN Parameters
    9. 6.9  CC PHY Parameters
    10. 6.10 Thermal Shutdown Characteristics
    11. 6.11 Oscillator Characteristics
    12. 6.12 ADC Characteristics
    13. 6.13 TVSP Parameters
    14. 6.14 Input/Output (I/O) Characteristics
    15. 6.15 BC1.2 Characteristics
    16. 6.16 I2C Requirements and Characteristics
    17. 6.17 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power Management and Supervisory Circuitry
        1. 8.3.1.1 VIN UVLO and Enable/UVLO
        2. 8.3.1.2 Internal LDO Regulators
      2. 8.3.2  TVSP Device Configuration and ESD Protection
      3. 8.3.3  External NFET and LSGD
      4. 8.3.4  Buck-Boost Regulator
        1. 8.3.4.1  Buck-Boost Regulator Operation
        2. 8.3.4.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 8.3.4.3  VIN Supply and VIN Over-Voltage Protection
        4. 8.3.4.4  Feedback Paths and Error Amplifiers
        5. 8.3.4.5  Transconductors and Compensation
        6. 8.3.4.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 8.3.4.7  VBUS Overvoltage Protection
        8. 8.3.4.8  VBUS Undervoltage Protection
        9. 8.3.4.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 8.3.4.10 Buck-Boost Peak Current Limits
      5. 8.3.5  USB-PD Physical Layer
        1. 8.3.5.1 USB-PD Encoding and Signaling
        2. 8.3.5.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.5.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.5.4 USB-PD BMC Transmitter
        5. 8.3.5.5 USB-PD BMC Receiver
        6. 8.3.5.6 Squelch Receiver
      6. 8.3.6  VCONN
      7. 8.3.7  Cable Plug and Orientation Detection
        1. 8.3.7.1 Configured as a Source
        2. 8.3.7.2 Configured as a Sink
        3. 8.3.7.3 Configured as a DRP
        4. 8.3.7.4 Overvoltage Protection (Px_CC1, Px_CC2)
      8. 8.3.8  ADC
        1. 8.3.8.1 ADC Divider Ratios
      9. 8.3.9  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      10. 8.3.10 DisplayPort Hot-Plug Detect (HPD)
      11. 8.3.11 USB2.0 Low-Speed Endpoint
      12. 8.3.12 Digital Interfaces
        1. 8.3.12.1 General GPIO
        2. 8.3.12.2 I2C Buffer
      13. 8.3.13 I2C Interface
        1. 8.3.13.1 I2C Interface Description
        2. 8.3.13.2 I2C Clock Stretching
        3. 8.3.13.3 I2C Address Setting
        4. 8.3.13.4 Unique Address Interface
        5. 8.3.13.5 I2C Pullup Resistor Calculation
      14. 8.3.14 Digital Core
        1. 8.3.14.1 Device Memory
        2. 8.3.14.2 Core Microprocessor
      15. 8.3.15 NTC Input
      16. 8.3.16 Thermal Sensors and Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application GUI Selections
        2. 9.2.2.2 EEPROM Selection
        3. 9.2.2.3 EN/UVLO
        4. 9.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 9.2.2.5 Inductor Currents
        6. 9.2.2.6 Output Capacitor
        7. 9.2.2.7 Input Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     106

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RQL|29
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Switching Frequency, Frequency Dither, Phase-Shift and Synchronization

The PWM oscillator frequency (fsw) is programmed by firmware using the application configuration GUI. The switching converter is intended for operation below the AM radio band (520 kHz - 1730 kHz). Three nominal fsw settings below are available: 300 kHz, 400 kHz and 450 kHz.

Frequency dithering can be enabled by firmware via the application GUI. When enabled, the nominal oscillator frequency is dithered by ±FSSS (approximately ±10%) using triangular waveform modulation (see Dithering using triangular waveform modulation). The dither period τM is the reciprocal of the dither modulation frequency FSSS_MOD. Two firmware selectable dither modulation frequencies FSSS_M are available: 10 and 25 kHz. Dithering spreads the spectral peaks generated by switching, thereby reducing the peak harmonic levels and easing EMI filter design.

TPS25763-Q1 Dithering Using Triangular Waveform
                    ModulationFigure 8-14 Dithering Using Triangular Waveform Modulation

Multiple converters can be synchronized using the SYNC pin. This pin can be firmware-configured as either an output SYNC(o) or an input SYNC(i).

  • SYNC(o): The switching clock is placed on the SYNC(o) pin. This waveform has a duty cycle of approximately 50%. If frequency dithering is configured by firmware, this signal also exhibits dithering. Four phase settings are available by firmware configuration to shift the SYNC(o) output relative to the internal switching clock by 0°, 90°, 120°, or 180°. SYNC(o) is used to drive an external DC/DC converter clock with the switching converter clock inside the TPS25763-Q1. When two dc/dc converters operate out of phase, peak input current from the battery is reduced and total input bulk capacitance requirements decrease.
    TPS25763-Q1 SYNC(o) Phase
                                Shift Figure 8-15 SYNC(o) Phase Shift
    TPS25763-Q1 Using SYNC(o) to
                                drive external DC/DC Converter Figure 8-16 Using SYNC(o) to drive external DC/DC Converter
  • SYNC(i): The internal clock is synchronized to the pulse train on the SYNC(i) pin. This feature is used to drive the TPS25763-Q1 with an external clock. The period of this clock must meet synchronization requirements in SYNC(i) frequency ranges or the TPS25763-Q1 instead uses its internal switching clock. If an external clock deviates outside of the acceptable frequency range and then returns to within the acceptable frequency range, the TPS25763-Q1 resumes operation from the external clock after counting 8 consecutive clocks meeting the criteria of Table 8-4. When SYNC(i) is configured, frequency dithering is disabled when operating from the internal clock following a failure of the external clock.

Table 8-4 SYNC(i) Frequency Ranges
fSW Firmware SettingAllowed SYNC(i) Frequency Range
MINMAX
300 kHz250 kHz353 kHz
400 kHz334 kHz470 kHz
450 kHz376 kHz530 kHz