SLVSGO0 October   2024 TPS25763-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Recommended Components
    5. 6.5  Thermal Information
    6. 6.6  Buck-Boost Regulator
    7. 6.7  CC Cable Detection Parameters
    8. 6.8  CC VCONN Parameters
    9. 6.9  CC PHY Parameters
    10. 6.10 Thermal Shutdown Characteristics
    11. 6.11 Oscillator Characteristics
    12. 6.12 ADC Characteristics
    13. 6.13 TVSP Parameters
    14. 6.14 Input/Output (I/O) Characteristics
    15. 6.15 BC1.2 Characteristics
    16. 6.16 I2C Requirements and Characteristics
    17. 6.17 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power Management and Supervisory Circuitry
        1. 8.3.1.1 VIN UVLO and Enable/UVLO
        2. 8.3.1.2 Internal LDO Regulators
      2. 8.3.2  TVSP Device Configuration and ESD Protection
      3. 8.3.3  External NFET and LSGD
      4. 8.3.4  Buck-Boost Regulator
        1. 8.3.4.1  Buck-Boost Regulator Operation
        2. 8.3.4.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 8.3.4.3  VIN Supply and VIN Over-Voltage Protection
        4. 8.3.4.4  Feedback Paths and Error Amplifiers
        5. 8.3.4.5  Transconductors and Compensation
        6. 8.3.4.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 8.3.4.7  VBUS Overvoltage Protection
        8. 8.3.4.8  VBUS Undervoltage Protection
        9. 8.3.4.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 8.3.4.10 Buck-Boost Peak Current Limits
      5. 8.3.5  USB-PD Physical Layer
        1. 8.3.5.1 USB-PD Encoding and Signaling
        2. 8.3.5.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.5.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.5.4 USB-PD BMC Transmitter
        5. 8.3.5.5 USB-PD BMC Receiver
        6. 8.3.5.6 Squelch Receiver
      6. 8.3.6  VCONN
      7. 8.3.7  Cable Plug and Orientation Detection
        1. 8.3.7.1 Configured as a Source
        2. 8.3.7.2 Configured as a Sink
        3. 8.3.7.3 Configured as a DRP
        4. 8.3.7.4 Overvoltage Protection (Px_CC1, Px_CC2)
      8. 8.3.8  ADC
        1. 8.3.8.1 ADC Divider Ratios
      9. 8.3.9  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      10. 8.3.10 DisplayPort Hot-Plug Detect (HPD)
      11. 8.3.11 USB2.0 Low-Speed Endpoint
      12. 8.3.12 Digital Interfaces
        1. 8.3.12.1 General GPIO
        2. 8.3.12.2 I2C Buffer
      13. 8.3.13 I2C Interface
        1. 8.3.13.1 I2C Interface Description
        2. 8.3.13.2 I2C Clock Stretching
        3. 8.3.13.3 I2C Address Setting
        4. 8.3.13.4 Unique Address Interface
        5. 8.3.13.5 I2C Pullup Resistor Calculation
      14. 8.3.14 Digital Core
        1. 8.3.14.1 Device Memory
        2. 8.3.14.2 Core Microprocessor
      15. 8.3.15 NTC Input
      16. 8.3.16 Thermal Sensors and Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application GUI Selections
        2. 9.2.2.2 EEPROM Selection
        3. 9.2.2.3 EN/UVLO
        4. 9.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 9.2.2.5 Inductor Currents
        6. 9.2.2.6 Output Capacitor
        7. 9.2.2.7 Input Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     106

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RQL|29
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1.1 VIN UVLO and Enable/UVLO

The TPS25763-Q1 has one internally fixed VIN UVLO and one user programmable UVLO using the EN/UVLO pin. Both thresholds must be cleared for the device to start up.

  • The fixed VIN(UVLO) has a rising threshold between 5 and 5.5 V to ensure internal circuits have sufficient headroom for proper operation.
  • The EN/UVLO pin provides the user with a resistor programmable UVLO threshold and master enable / disable for the device.

The EN/UVLO pin has three distinct voltage ranges: shutdown, standby, and operating. When the EN/UVLO pin is below the standby threshold VEN(STBY), the device is disabled in a low power shutdown. When EN/UVLO voltage is greater than the standby threshold VEN(STBY) but less than the operating threshold VEN(OPER), the internal bias rails, LDO_5V, LDO_3V3, and LDO_1V5 regulators are enabled but remaining device functions are disabled. When EN/UVLO is greater than the operating threshold VEN(OPER) and LDO_5V, LDO_3V3 and LDO_1V5 regulators are above their respective undervoltage threshold UVLO thresholds, the device is fully functional. The EN/UVLO pin includes fixed hysteresis between the shutdown mode and the standby mode.

TPS25763-Q1
Figure 8-1 EN/UVLO and LDO Sequencing
TPS25763-Q1
Table 8-1 EN/UVLO and LDO_UVLO Operation
EN/UVLO (1) LDOs DEVICE OPERATION
VEN/UVLO < VEN(LDO_V5V_F) — Shutdown: LDO_5V, LDO_3V3 and LDO_1V5 OFF. M0 (MCU) is OFF.
VEN(LDO_V5V_R) < VEN/UVLO < VEN(STBY) — Standby: LDO_5V, LDO_3V3 and LDO_1V5 ON. M0 (MCU) is OFF.
VEN/UVLO > VEN(OPER) LDO_5V < VLDO_5V(UVLO_R), or LDO_3V3 < VLDO_3V3(UVLO_R); or LDO_1V5 < VLDO_1V5(UVLO_R) LDO_5V, LDO_3V3 and LDO_1V5 ON, M0 (MCU) is OFF.
VEN/UVLO > VEN(OPER) LDO_5V > VLDO_5V(UVLO_R), and LDO_3V3 > VLDO_3V3(UVLO_R), and LDO_1V5 > VLDO_1V5(UVLO_R) Operating: M0 (MCU) is ON.
(1) Valid when VIN > VIN(UVLO_R).

In some cases an input UVLO level different than that provided by the internal VIN(UVLO) is needed and can be accomplished by using the circuit shown in UVLO Threshold Programming. The input voltage at which the device turns on is designated VON; while the turnoff voltage is VOFF. First a value for RENB is chosen in the range of 13 kΩ to 22 kΩ. Use Equation 3 and Equation 7 to calculate RENT and VOFF.

TPS25763-Q1 UVLO Threshold Programming Figure 8-2 UVLO Threshold Programming

Equation 1. R E N T = V O N V E N ( O P E R ) - 1 × R E N B

The hysteresis between the UVLO turn-on threshold and turn-off threshold is set by the upper resistor in the EN/UVLO resistor divider and is given by:

Equation 2. V O F F = 1 - V E N ( H Y S ) V E N ( O P E R ) × V O N

Where

  • VON = VIN turn-on voltage
  • VOFF = VIN turn-off voltage
Note: Ensure RENT ≥ 47 kΩ

If the programmable UVLO is not required, the EN/UVLO pin can be connected to the IN pin with a 47 kΩ, or larger, resistor.