SBVS426B December   2022  – October 2024 TPS25772-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Recommended Components
    5. 6.5  Thermal Information
    6. 6.6  Buck-Boost Regulator
    7. 6.7  CC Cable Detection Parameters
    8. 6.8  CC VCONN Parameters
    9. 6.9  CC PHY Parameters
    10. 6.10 Thermal Shutdown Characteristics
    11. 6.11 Oscillator Characteristics
    12. 6.12 ADC Characteristics
    13. 6.13 TVSP Parameters
    14. 6.14 Input/Output (I/O) Characteristics
    15. 6.15 BC1.2 Characteristics
    16. 6.16 I2C Requirements and Characteristics
    17. 6.17 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power Management and Supervisory Circuitry
        1. 8.3.1.1 VIN UVLO and Enable/UVLO
        2. 8.3.1.2 Internal LDO Regulators
      2. 8.3.2  TVSP Device Configuration and ESD Protection
      3. 8.3.3  Buck-Boost Regulator
        1. 8.3.3.1  Buck-Boost Regulator Operation
        2. 8.3.3.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 8.3.3.3  VIN Supply and VIN Over-Voltage Protection
        4. 8.3.3.4  Feedback Paths and Error Amplifiers
        5. 8.3.3.5  Transconductors and Compensation
        6. 8.3.3.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 8.3.3.7  VBUS Overvoltage Protection
        8. 8.3.3.8  VBUS Undervoltage Protection
        9. 8.3.3.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 8.3.3.10 Buck-Boost Peak Current Limits
      4. 8.3.4  USB-PD Physical Layer
        1. 8.3.4.1 USB-PD Encoding and Signaling
        2. 8.3.4.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.4.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.4.4 USB-PD BMC Transmitter
        5. 8.3.4.5 USB-PD BMC Receiver
        6. 8.3.4.6 Squelch Receiver
      5. 8.3.5  VCONN
      6. 8.3.6  Cable Plug and Orientation Detection
        1. 8.3.6.1 Configured as a Source
        2. 8.3.6.2 Configured as a Sink
        3. 8.3.6.3 Overvoltage Protection (Px_CC1, Px_CC2)
      7. 8.3.7  ADC
        1. 8.3.7.1 ADC Divider Ratios
      8. 8.3.8  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      9. 8.3.9  USB2.0 Low-Speed Endpoint
      10. 8.3.10 Digital Interfaces
        1. 8.3.10.1 General GPIO
        2. 8.3.10.2 I2C Buffer
      11. 8.3.11 I2C Interface
        1. 8.3.11.1 I2C Interface Description
        2. 8.3.11.2 I2C Clock Stretching
        3. 8.3.11.3 I2C Address Setting
        4. 8.3.11.4 Unique Address Interface
        5. 8.3.11.5 I2C Pullup Resistor Calculation
      12. 8.3.12 Digital Core
        1. 8.3.12.1 Device Memory
        2. 8.3.12.2 Core Microprocessor
      13. 8.3.13 NTC Input
      14. 8.3.14 Thermal Sensors and Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application GUI Selections
        2. 9.2.2.2 EEPROM Selection
        3. 9.2.2.3 EN/UVLO
        4. 9.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 9.2.2.5 Inductor Currents
        6. 9.2.2.6 Output Capacitor
        7. 9.2.2.7 Input Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     103

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RQL|29
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

TPS25772-Q1 RQL Package29-Pin (VQFN)Top View Figure 5-1 RQL Package29-Pin (VQFN)Top View
Table 5-1 Pin Descriptions
PIN DESCRIPTION
NAME NO.
EN/UVLO 6 Enable pin. For EN/UVLO < 0.3 V, the TPS25772-Q1 is in a low current shutdown mode. For EN/UVLO > 1.3 V, the full functionality is enabled, provided LDO_5V exceeds the LDO_5V UVLO threshold.
IN 15 The input supply pin to the IC. Connect VIN to a supply voltage between 5.5 V and 18 V (40-V ABS MAX transient).
PGND 13 Power ground of the IC. The high current ground connection to the low-side gate drivers.
SW1 14 The buck side switching node.
SW2 12 The boost side switching node.
BOOT1 16 An external capacitor is required between the BOOT1 and the SW1 pins to provide bias to the high-side MOSFET gate drivers.
BOOT2 10 An external capacitor is required between the BOOT2 and the SW2 pins to provide bias to the high-side MOSFET gate drivers.
AGND 5 Analog ground of the IC.
OUT 11 Output of the buck-boost regulator. Connect to bulk capacitance.
CSP 28 Positive input of the current sense amplifier.
CSN/BUS 29 Negative input of the current sense amplifier. This is the PA_VBUS supply.
LDO_5V 21 Output of internal 5 V LDO for buck-boost low-side FET drivers, and Px_VCONN supply. Connect bypass capacitor to PGND. May be overdriven from external 5-V supply.
LDO_3V3 27 Output of internal 3.3-V LDO for analog circuitry and GPIO drivers. Connect bypass capacitor to AGND.
LDO_1V5 7 Output of internal 1.5-V LDO for digital circuitry. Connect bypass capacitor to AGND.
I2C_SCL1 3 Controller I2C Clock Input/Output.
I2C_SDA1 4 Controller I2C Data Input/Output.
GPIO2 (I2C_SCL2 or PB_DP) 25 Multifunction pin. GPIO; target I2C Clock Input; or Port B USB data line DP input depending upon firmware configuration.
GPIO3 (I2C_SDA2 or PB_DM) 26 Multifunction pin. GPIO; target I2C Data Input; or Port B USB data line DM input depending upon firmware configuration.
IRQ (GPIO9) 2 Multifunction pin. Interrupt I/O and fault flag for I2C1 or I2C2; or GPIO depending upon firmware configuration. Reports fault conditions set by application configuration firmware.
PA_CC1 20 Analog input/output. Port A Type-C current advertisement, VCONN, and USB PD modem. Connect to Port A Type-C connector CC1 pin.
PA_CC2 19 Analog input/output. Port A Type-C current advertisement, VCONN, and USB PD modem. Connect to Port A Type-C connector CC2 pin.
PA_DP (GPIO8) 18 Multifunction pin. BC1.2 USB 2.0 D+ data line input/output. Connect to Port A Type-C USB data line DP connector pins. May also be used as GPIO depending upon firmware configuration.
PA_DM (GPIO7) 17 Multifunction pin. BC1.2 USB 2.0 D- data line input/output. Connect to Port A Type-C USB data line DM connector pins. May also be used as GPIO depending upon firmware configuration.
PB_CC1 (GPIO0 ) 23 Multifunction pin. Port B Type-C current advertisement, VCONN, and USB PD modem. Connect to Port B Type-C connector CC1 pin; May also be used as GPIO when port B is disabled in firmware configuration.
PB_CC2 ( GPIO1 or IRQ2(o)) 24 Multifunction pin. Port B Type-C current advertisement, VCONN, and USB PD modem. Connect to Port B Type-C connector CC2 pin; May also be used as GPIO or Interrupt I/O when port B is disabled in firmware configuration.
GPIO5 (NTC) 8 Multifunction pin. GPIO; thermistor input (can use either negative temperature coefficient resistor or positive temperature coefficient resistor).
GPIO6 (SYNC) 1 Multifunction pin. GPIO; SYNC(o) - clock out to synchronize external DC/DC regulators to internal DC/DC switching frequency; SYNC(i) - clock input to synchronize internal DC/DC to an external clock.
PB_VBUS (GPIO4) 9 Multifunction pin. PB_VBUS voltage monitor; or GPIO when port B is disabled in firmware configuration
TVSP 22 Transient voltage protection and firmware setting pin. See TVSP Device Configuration and ESD Protection for boot configuration and R-C network component values.