SBVS426B December   2022  – October 2024 TPS25772-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Recommended Components
    5. 6.5  Thermal Information
    6. 6.6  Buck-Boost Regulator
    7. 6.7  CC Cable Detection Parameters
    8. 6.8  CC VCONN Parameters
    9. 6.9  CC PHY Parameters
    10. 6.10 Thermal Shutdown Characteristics
    11. 6.11 Oscillator Characteristics
    12. 6.12 ADC Characteristics
    13. 6.13 TVSP Parameters
    14. 6.14 Input/Output (I/O) Characteristics
    15. 6.15 BC1.2 Characteristics
    16. 6.16 I2C Requirements and Characteristics
    17. 6.17 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power Management and Supervisory Circuitry
        1. 8.3.1.1 VIN UVLO and Enable/UVLO
        2. 8.3.1.2 Internal LDO Regulators
      2. 8.3.2  TVSP Device Configuration and ESD Protection
      3. 8.3.3  Buck-Boost Regulator
        1. 8.3.3.1  Buck-Boost Regulator Operation
        2. 8.3.3.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 8.3.3.3  VIN Supply and VIN Over-Voltage Protection
        4. 8.3.3.4  Feedback Paths and Error Amplifiers
        5. 8.3.3.5  Transconductors and Compensation
        6. 8.3.3.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 8.3.3.7  VBUS Overvoltage Protection
        8. 8.3.3.8  VBUS Undervoltage Protection
        9. 8.3.3.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 8.3.3.10 Buck-Boost Peak Current Limits
      4. 8.3.4  USB-PD Physical Layer
        1. 8.3.4.1 USB-PD Encoding and Signaling
        2. 8.3.4.2 USB-PD Bi-Phase Marked Coding
        3. 8.3.4.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 8.3.4.4 USB-PD BMC Transmitter
        5. 8.3.4.5 USB-PD BMC Receiver
        6. 8.3.4.6 Squelch Receiver
      5. 8.3.5  VCONN
      6. 8.3.6  Cable Plug and Orientation Detection
        1. 8.3.6.1 Configured as a Source
        2. 8.3.6.2 Configured as a Sink
        3. 8.3.6.3 Overvoltage Protection (Px_CC1, Px_CC2)
      7. 8.3.7  ADC
        1. 8.3.7.1 ADC Divider Ratios
      8. 8.3.8  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      9. 8.3.9  USB2.0 Low-Speed Endpoint
      10. 8.3.10 Digital Interfaces
        1. 8.3.10.1 General GPIO
        2. 8.3.10.2 I2C Buffer
      11. 8.3.11 I2C Interface
        1. 8.3.11.1 I2C Interface Description
        2. 8.3.11.2 I2C Clock Stretching
        3. 8.3.11.3 I2C Address Setting
        4. 8.3.11.4 Unique Address Interface
        5. 8.3.11.5 I2C Pullup Resistor Calculation
      12. 8.3.12 Digital Core
        1. 8.3.12.1 Device Memory
        2. 8.3.12.2 Core Microprocessor
      13. 8.3.13 NTC Input
      14. 8.3.14 Thermal Sensors and Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application GUI Selections
        2. 9.2.2.2 EEPROM Selection
        3. 9.2.2.3 EN/UVLO
        4. 9.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 9.2.2.5 Inductor Currents
        6. 9.2.2.6 Output Capacitor
        7. 9.2.2.7 Input Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     103

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RQL|29
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2 TVSP Device Configuration and ESD Protection

The Transient Voltage protection and firmware Setting Pin (TVSP) has three functions: 1) Boot configuration settings; 2) USB connector pin short to VBUS or VBAT protection; and 3) USB connector pin enhanced ESD protection.

  • RTVSP: At power on, the resistance between the TVSP pin and PGND determines the boot method, USB PD port I2C addresses and I2C logic thresholds. Resistor values are device-specific; refer to Table 8-6. The most common configuration is shown in Basic TVSP Pin Connection with RTVSP open, corresponding to TVSP Index 0. During device initialization and boot, typically within 4 seconds after power on, VIN must be above 7.6 V to ensure proper bias of the TVSP pin to 5.5 V. Once boot is complete the device can operate over the full VIN range.
  • CTVSP: A 0.1-µF capacitor (CTVSP) must be connected to PGND. Place CTVSP as close to the TVSP pin as possible to minimize parasitic inductance. CTVSP is part of the centralized protection circuitry fortifying connector pins Px_CCy, Px_DP and Px_DM from damage during short to VBUS, VBAT and ESD events. A 40-V 0.1-µF capacitor is recommended for proper operation of the internal TVSP regulator circuit.
  • TVSP Damper Network: Capacitance, CDAMP, and resistance, RDAMP, form an RC network preventing excessive current from flowing inside the device during connector pin over-voltage and ESD events.
    • CDAMP: A 0.47-µF capacitor must be connected in series with RDAMP to PGND. A 40-V 0.47-µF capacitor is recommended.
    • RDAMP: A 10-Ω resistor must be connected in series with CDAMP to PGND. A 0.25-W rating is recommended.

TPS25772-Q1 Basic TVSP Pin Connection Figure 8-4 Basic TVSP Pin Connection
Table 8-3 Recommended TVSP Components
CTVSP RDAMP CDAMP
0.1 μF 10 Ω 0.47 μF
Table 8-4 RTVSP Configuration Settings (TPS257xxCQRQLRQ1)
RTVSP (kΩ) (1) TVSP Index ADC Value I2C Target Port Addresses (A | B)(2) I2C Logic (VDD) Boot Mode
Open 0 ≤ 10 (0x0A) 0x22 | 0x26 3.3 V EEPROM
93.1 1 ≤ 24 (0x18) 0x23 | 0x27 3.3 V External HUB/MCU
47.5 2 ≤ 42 (0x2A) 0x22 | 0x26 1.8 V EEPROM
29.4 3 ≤ 63 (0x3F) 0x23 | 0x27 1.8 V External HUB/MCU
20.0 4 ≤ 89 (0x59) 0x23 | 0x27 3.3 V EEPROM
14.7 5 ≤ 119 (0x77) 0x22 | 0x26 3.3 V External HUB/MCU
11.0 6 ≤ 156 (0x9C) 0x23 | 0x27 1.8 V EEPROM
8.45 7 ≤ 201 (0xC9) 0x22 | 0x26 1.8 V External HUB/MCU
6.65 8 ≤ 255 (0xFF) 0x22 | 0x26 3.3 V Firmware Update
Table 8-5 RTVSP Configuration Settings (TPS257xxCAQRQLRQ1)
RTVSP (kΩ) TVSP Index ADC Value I2C Target Port Addresses (A | B) I2C Logic (VDD) Boot Mode
Open 0 ≤ 10 (0x0A) 0x22 | 0x26 3.3 V EEPROM
5.6 8 ≤ 255 (0xFF) 0x22 | 0x26 3.3 V Firmware Update
Table 8-6 RTVSP Configuration Settings (TPS257xxDQRQLRQ1)
RTVSP (kΩ) (1) TVSP Index ADC Value I2C Target Port Addresses (A | B)(2) I2C Logic (VDD) Boot Mode
Open 0 ≤ 10 (0x0A) 0x22 | 0x26 3.3 V EEPROM
93.1 1 ≤ 24 (0x18) 0x23 | 0x27 3.3 V External HUB/MCU
47.5 2 ≤ 42 (0x2A) 0x22 | 0x26 1.8 V EEPROM
26.7 3 ≤ 63 (0x3F) 0x23 | 0x27 1.8 V External HUB/MCU
18.2 4 ≤ 89 (0x59) 0x23 | 0x27 3.3 V EEPROM
13.0 5 ≤ 119 (0x77) 0x22 | 0x26 3.3 V External HUB/MCU
9.53 6 ≤ 156 (0x9C) 0x23 | 0x27 1.8 V EEPROM
7.5 7 ≤ 201 (0xC9) 0x22 | 0x26 1.8 V External HUB/MCU
5.6 8 ≤ 255 (0xFF) 0x22 | 0x26 3.3 V Firmware Update
(1) 1% resistor required.
(2) 0x22h = 0100010; 0x26h = 0100110; 0x23h = 0100011; 0x27 = 0100111

For the TPS25772D-Q1 device, a factory-programmed default application configuration is applied at power-up. The default configuration is applied when the boot mode is configured for EEPROM and the EEPROM configuration is not loaded; for example when the image provided by the EEPROM is not valid or the EEPROM is not connected. When the default application configuration is loaded, the maximum port output power (port PDP) is configured using the TVSP index as defined by RTVSP. Valid TVSP indexes for this mode of operation are shown in R TVSP Port Maximum PDP Selection (TPS25762DQRQLRQ1 and TPS25772DQRQLRQ1).

Table 8-7 RTVSP Port Maximum PDP Selection (TPS25762DQRQLRQ1 and TPS25772DQRQLRQ1)
RTVSP (kΩ) TVSP Index ADC Value I2C Target Port Addresses (A | B) I2C Logic (VDD) Port Maximum PDP
Open 0 ≤ 10 (0x0A) 0x22 | 0x26 3.3 V 60 W
47.5 2 ≤ 42 (0x2A) 0x22 | 0x26 1.8 V 45 W
18.2 4 ≤ 89 (0x59) 0x23 | 0x27 3.3 V 27 W
9.53 6 ≤ 156 (0x9C) 0x23 | 0x27 1.8 V 15 W

The device settings when the default application configuration is loaded are defined by Table 8-8.

Table 8-8 Default Application Configuration (TPS25762DQRQLRQ1 and TPS25772DQRQLRQ1)
Parameter TPS25762DQRQLRQ1 TPS25772DQRQLRQ1 Comment
XID 0x00 0x00
PID 0x00 0x00
VID 0x0451 0x0451 TI VID
Port Min Power 7.5W 7.5W Applies to all ports
Port Max Power 60W/45W/27W/15W 60W/45W/27W/15W Set by TVSP Index; applies to all ports
System Max Power 60W/45W/27W/15W Port Max Power x 2
Port PPS Enabled Enabled Applies to all ports
SPM Power Policy n/a Assured Capacity
BC1.2 Enabled Enabled Applies to all ports
External DCDC n/a TPS55288-Q1
Port A ILIM Overshoot 400 mA 400 mA
Port A APDO ILIM Overshoot 50 mA 50 mA
Port A Cable Compensation Disabled Disabled
Port A High ILIM Delay Enabled Enabled
Port B ILIM Overshoot n/a 400 mA
Port B APDO ILIM Overshoot n/a 50 mA
Port B Cable Compensation n/a External Set by external DCDC
Port B VBUS Boost n/a 0.1 V
Port B Discharge n/a Enabled External, controlled by GPIO9
Internal DCDC Freq 400 kHz 400 kHz
Internal DCDC Dither 10 Hz 10 Hz
Grace Period Power ON 15 min 15 min
Grace Period Power OFF 15 min 15 min
Range 3 Power FULL FULL
Range 2 Power 60% 60% % of System Max Power
Range 1 to 2 Rising Threshold 8.96 V 8.96 V Measured at VIN
Range 2 to 1 Falling Threshold 7.04 V 7.04 V Measured at VIN
Range 2 to 3 Rising Threshold 11.52 V 11.52 V Measured at VIN
Range 3 to 2 Falling Threshold 10.08 V 10.08 V Measured at VIN
Thermal Foldback Enabled Enabled NTC/PTC configuration
Phase 1 Max Power 60% 60% % of System Max Power
Phase 1 Rising Threshold 2.044 V 2.044 V
Phase 1 Falling Threshold 1.988 V 1.988 V
Phase 2 Max Power 30% 30% % of System Max Power
Phase 2 Rising Threshold 2.1 V 2.1 V
Phase 2 Falling Threshold 2.044 V 2.044 V
Phase 3 Max Power 0% 0% % of System Max Power
Phase 3 Rising Threshold 2.142 V 2.142 V
Phase 3 Falling Threshold 2.086 V 2.086 V

Applications requiring a configuration other than TVSP Index 0 (RTVSP open), as shown in R TVSP Configuration Settings (TPS257xxCQRQLRQ1) and R TVSP Configuration Settings (TPS257xxDQRQLRQ1) must implement a circuit similar to the one shown in Figure 8-5. The base of the bipolar transistor is connected to LDO_5V to provide proper power up sequencing of the TVSP resistor - OFF when TPS25772-Q1 is disabled and ON when TPS25772-Q1 is enabled. A 2N2222 is recommended for its large collector-emitter breakdown voltage, low-cost and wide availability.

TPS25772-Q1 RTVSP Circuit Configuration Figure 8-5 RTVSP Circuit Configuration

Device firmware can be updated using the USB Endpoint on the PA_DP and PA_DM pins. To enable firmware update mode, boot the device with a resistance corresponding to TVSP Index 8 between TVSP and PGND. A boot cycle can be performed by power cycling the device or by pulling the EN/UVLO pin momentarily below the VEN(OPER) threshold. An example circuit to enable USB Endpoint firmware update mode is shown in Figure 8-6.

TPS25772-Q1 Example Circuit to Enable USB Endpoint Firmware Update Mode Figure 8-6 Example Circuit to Enable USB Endpoint Firmware Update Mode