10.1 Layout Guidelines

Layout best practices as it applies to the TPS25810 are listed below.

• For all applications a 10-µF ceramic capacitor is recommended near the Type-C receptacle and another 120-µF ceramic capacitor close to IN1 pin.
  • The optimum placement of the 120-µF capacitor is closest to the IN1 and GND pins of the device.
  • Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN1 pin, and the GND pin of the IC. See Figure 29 for a PCB layout example.
• High current carrying power path connections to the device should be as short as possible and should be sized to carry at least twice the full-load current.
  • Have the input and output traces as short as possible. The most common cause of voltage drop failure in USB power delivery is the resistance associated with the VBUS trace. Trace length, maximum current being supplied for normal operation, and total resistance associated with the VBUS trace must be taken into account while budgeting for voltage drop.
  • For example, a power carrying trace that supplies 3 A, at a distance of 20 inches, 0.100-in. wide, with 2-oz. copper on the outer layer will have a total resistance of approximately 0.046 Ω and voltage drop of 0.14 V. The same trace at 0.050-in.-wide will have a total resistance of approximately 0.09 Ω and voltage drop of 0.28 V.
  • Make power traces as wide as possible.
• The resistor attached to the REF pin of the device has several requirements:
  • It is recommended to use a 1% 100-kΩ low tempco resistor.
  • It should be connected to pins REF and REF_RTN (pin 9 and pin 10 respectively).
  • The REF_RTN pin should be isolated from the GND plane. See Figure 29.
  • The trace routing between the REF and REF_RTN pins of the device should be as short as possible to reduce parasitic effects on current limit and current advertisement accuracy. These traces should not have any coupling to switching signals on the board.
• Locate all TPS25810 pull-up resistors for open-drain outputs close to their connection pin. Pull up resistors should be 100 kΩ.
  • When a particular open drain output is not used/needed in the system leave the associated pin open or tied to GND.
• Keep the CC lines close to the same length.
• Thermal Considerations:
  • When properly mounted, the thermal pad package provides significantly greater cooling ability than an ordinary package. To operate at rated power, the thermal pad must be soldered to the board GND plane directly under the device. The thermal pad is at GND potential and can be connected using multiple vias to inner layer GND. Other planes, such as the bottom side of the circuit board can be used to increase heat sinking in higher current applications. Refer to Technical Briefs: PowerPad™ Thermally Enhanced Package (TI literature Number SLMA002) and PowerPAD™ Made Easy (TI Literature Number SLMA004) or more information on using this thermal pad package.
  • The thermal via land pattern specific to the TPS25810 can be downloaded from the device web page at www.ti.com.
  • Obtaining acceptable performance with alternate layout schemes is possible; however the layout example in the following section has been shown to produce good results and is intended as a guideline.
• ESD Considerations
  • TPS25810 has built in ESD protection for CC1 and CC2. Keep trace length to a minimum from the type-C receptacle to the TPS25810 on CC1 and CC2.
  • 10-uF output cap should be placed near Type-C receptacle
  • Refer to the TPS25810EVM-745 Evaluation Module for an example of a double layer board that passes IEC61000-4-2 testing
  • Do not create stubs or test points on the CC lines. Keep the traces short if possible and use minimal via along the traces (1-2 inches or less).
  • Refer to ESD Protection Layout Guide for additional information (TI Literature Number SLVA680)
  • Have a dedicated ground plane layer if possible to avoid differential voltage buildup

10.2 Layout Example

Figure 29. Layout Example