SLVSE37 April   2017 TPS25810A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 USB Type-C Basic
      2. 8.1.2 Configuration Channel
      3. 8.1.3 Detecting a Connection
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Configuration Channel Pins CC1 and CC2
      2. 8.3.2 Current Capability Advertisement and Overload Protection
      3. 8.3.3 Undervoltage Lockout (UVLO)
        1. 8.3.3.1  Device Power Pins (IN1, IN2, AUX, OUT, and GND)
        2. 8.3.3.2  FAULT Response
        3. 8.3.3.3  Thermal Shutdown
        4. 8.3.3.4  REF
        5. 8.3.3.5  Audio Accessory Detection
        6. 8.3.3.6  Debug Accessory Detection
        7. 8.3.3.7  Plug Polarity Detection
        8. 8.3.3.8  Device Enable Control
        9. 8.3.3.9  Cable Compensation (CS)
        10. 8.3.3.10 Power Wake
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Type-C DFP Port Implementation Without BC 1.2 Support
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Input and Output Capacitance
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Type-C DFP Port Implementation With BC 1.2 (DCP Mode) Support
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
      2. 12.2.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RVC|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS25810A-Q1 device is a Type-C DFP controller that supports all Type-C DFP required functions. It applies power to VBUS when a UFP attach is detected and removes power when it detects the UFP is detached. The device exposes its identity via its CC pin, advertising its current capability based on the CHG and CHG_HI pin settings. The TPS25810A-Q1 device also limits its advertised current internally and provides robust protection to a fault on the system VBUS power rail.

After a connection is established, either device is capable of providing VCONN to power circuits in the cable plug on the CC pin that is not connected to the CC wire in the cable. VCONN is internally current-limited and has its own supply pin, IN2. Apart from providing charging current to a UFP, the TPS25810A-Q1 device also supports audio and debug accessory modes.

The following design procedure can be used to implement a full-featured Type-C DFP.

NOTE

BC 1.2 is not supported in the TPS25810A-Q1 device. To support BC 1.2 with Type-C charging modes in a single Type-C connector, a dedicated charging port (DCP) controller something like a TPS2514A-Q1 device must be used.

9.2 Typical Applications

9.2.1 Type-C DFP Port Implementation Without BC 1.2 Support

Figure 19 shows a minimal Type-C DFP implementation capable of supporting 5-V and 3-A charging.

TPS25810A-Q1 typ_app_SLVSE37.gif Figure 19. Type-C DFP Port Implementation Without BC 1.2 Support

9.2.1.1 Design Requirements

9.2.1.1.1 Input and Output Capacitance

Input and output capacitance improves the performance of the device. The actual capacitance should be optimized for the particular application. For all applications, a 0.1-μF or greater ceramic bypass capacitor between INx and GND is recommended as close to the device as possible for local noise decoupling.

All protection circuits, including those of the TPS25810A-Q1 device, have the potential for input voltage overshoots and output voltage undershoots. Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input voltage in conjunction with input power-bus inductance and input capacitance when the INx pin is high-impedance (before turnon). Theoretically, the peak voltage is 2 times the applied voltage. The second cause is due to the abrupt reduction of output short-circuit current when the device turns off and energy stored in the input inductance drives the input voltage high. Input voltage droops may also occur with large load steps and as the output is shorted. Applications with large input inductance (for instance, connecting the evaluation board to the bench power supply through long cables) may require large input capacitance to prevent the voltage overshoot from exceeding the absolute maximum voltage of the device.

The fast current-limit speed of the TPS25810A-Q1 device to hard output short circuits isolates the input bus from faults. However, ceramic input capacitance in the range of 1 μF to 22 μF adjacent to the input aids in both response time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V are permitted. Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred and the device has abruptly reduced the OUT current. Energy stored in the inductance drives the OUT voltage down, and potentially negative, as it discharges. An application with large output inductance (such as from a cable) benefits from the use of a high-value output capacitor to control voltage undershoot.

When implementing a USB-standard application, 120-μF minimum output capacitance is required. Typically, a 150-μF electrolytic capacitor is used, which is sufficient to control voltage undershoots. Because in Type-C applications, DFP is a cold socket when no UFP is attached, the output capacitance should be placed at the INx pin versus the OUT pin, as is done in USB Type-A ports. It is also recommended to put a 10-μF ceramic capacitor on the OUT pin for better voltage bypass.

9.2.1.2 Detailed Design Procedure

The TPS25810A-Q1 device supports up to three different input voltages, based on the application. In the simplest implementation, all input pins are tied to a single voltage source set to 5 V, as shown in Figure 19. However, it is recommended to set a slightly higher (100 mV to 200 mV) input voltage, when possible, to compensate for IR loss from the source to the Type-C connector.

Other design considerations are listed as follows:

  • Place at least 120 µF of bypass capacitance close to the INx pins rather than the OUT pin, as Type-C is a cold-socket connector.
  • A 10-µF bypass capacitor is recommended to be placed near a Type-C receptacle VBUS pin to handle load transients.
  • Depending on the maximum current-level advertisement supported by the Type-C port in the system, set the CHG and CHG_HI levels accordingly. Advertisement of 3 A is shown in Figure 19.
  • The EN, CHG, and CHG_HI pins can be tied directly to GND or VAUX without a pullup resistor.
    • CHG and CHG_HI can also be dynamically controlled by a microcontroller to change the current advertisement level to the UFP.
  • When an open-drain output of the TPS25810A-Q1 device is not used, it can be left open or tied to GND.
  • Use a 1% 100-kΩ resistor to connect between the REF and REF_RTN pins, placing it close to the device pin and keeping it isolated from switching noise on the board.

9.2.1.3 Application Curves

TPS25810A-Q1 G001_slvscr1.gif
Basic start-up: IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V
CC1 = Rd CC2 = open
Figure 20. Basic Start-Up
TPS25810A-Q1 G003_slvscr1.gif
IN1 = IN2 = AUX = EN = 5 V; CHG = CHG_HI = 0 V
CC1 = open CC2 = Rd OUT = open → 5 Ω
Figure 22. Load Step
TPS25810A-Q1 G005_slvscr1.gif
IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V
CC1 = short CC2 = Rd
Figure 24. Short On CC1
TPS25810A-Q1 G007_slvscr1.gif
VIN 5 V → 3.5 V (100 ms) → 5 V (1 V/ms) CC1 = Rd
IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V CC2 = Ra
Figure 26. Brown-Out Test
TPS25810A-Q1 G002_slvscr1.gif
IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V
CC1 = open CC2 = open → Rd
Figure 21. Start-Up
TPS25810A-Q1 G004_slvscr1.gif
IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V
CC1 = Rd CC2 = open OUT = shorted
Figure 23. Hot-Plug to Short
TPS25810A-Q1 G006_slvscr1.gif
IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V
CC1 = Rd → open CC2 = open
Figure 25. Remove Rd

9.2.2 Type-C DFP Port Implementation With BC 1.2 (DCP Mode) Support

Figure 27 shows a Type-C DFP implementation capable of supporting 5-V, 3-A charging in a Type-C port that is also able to support charging of legacy devices when used with a Type-C µB cable assembly for charging phones and handheld devices equipped with a µB connector.

This implementation requires the use of a TPS2514A-Q1 device, a USB dedicated charging-port (DCP) controller with auto-detect feature to charge not only BC 1.2-compliant handheld devices but also popular phones and tablets that incorporate their own propriety charging algorithm. See TPS2513A-Q1, TPS2514A-Q1 USB Dedicated Charging Port Controller for more details.

TPS25810A-Q1 typ_app2_SLVSE37.gif Figure 27. Type-C DFP Port Implementation With BC 1.2 (DCP Mode) Support

9.2.2.1 Design Requirements

See Design Requirements for the design requirements.

9.2.2.2 Detailed Design Procedure

See Detailed Design Procedure for the detailed design procedure.

9.2.2.3 Application Curves

See Application Curves for the application curves.