SLVSEG3E September   2019  – March 2022 TPS25840-Q1 , TPS25842-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Buck Regulator
      2. 10.3.2  Enable/UVLO
      3. 10.3.3  Switching Frequency and Synchronization (RT/SYNC)
      4. 10.3.4  Spread-Spectrum Operation
      5. 10.3.5  VCC, VCC_UVLO
      6. 10.3.6  Minimum ON-time, Minimum OFF-time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Bootstrap Voltage (BOOT)
      9. 10.3.9  RSNS, RSET, RILIMIT and RIMON
      10. 10.3.10 Overcurrent and Short Circuit Protection
        1. 10.3.10.1 Current Limit Setting using RILIMIT
        2. 10.3.10.2 Buck Average Current Limit Design Example
        3. 10.3.10.3 External MOSFET Gate Drivers
        4. 10.3.10.4 Cycle-by-Cycle Buck Current Limit
      11. 10.3.11 Overvoltage, IEC and Short-to-Battery Protection
        1. 10.3.11.1 V BUS and V CSN/OUT Overvoltage Protection
        2. 10.3.11.2 DP_IN and DM_IN Protection
      12. 10.3.12 Cable Compensation
        1. 10.3.12.1 Cable Compensation Design Example
      13. 10.3.13 USB Port Control
      14. 10.3.14 FAULT Response
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 Device Power Pins (IN, CSN/OUT, and PGND)
      17. 10.3.17 Thermal Shutdown
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
      3. 10.4.3 Device Truth Table (TT)
      4. 10.4.4 USB Port Operating Modes
        1. 10.4.4.1 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
        2. 10.4.4.2 Charging Downstream Port (CDP) Mode
        3. 10.4.4.3 Client Mode
      5. 10.4.5 High-bandwidth Data-line Switches
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1  Output Voltage
        2. 11.2.2.2  Switching Frequency
        3. 11.2.2.3  Inductor Selection
        4. 11.2.2.4  Output Capacitor Selection
        5. 11.2.2.5  Input Capacitor Selection
        6. 11.2.2.6  Bootstrap Capacitor Selection
        7. 11.2.2.7  VCC Capacitor Selection
        8. 11.2.2.8  Enable and Under Voltage Lockout Set-Point
        9. 11.2.2.9  Current Limit Set-Point
        10. 11.2.2.10 Cable Compensation Set-Point
        11. 11.2.2.11 FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Ground Plane and Thermal Considerations
    3. 13.3 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 Support Resources
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.3.12 Cable Compensation

When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered to the load. Cable droop compensation linearly increases the voltage at the CSN/OUT pin of TPS2584x-Q1 as load current increases with the objective of maintaining VBUS_CON (the bus voltage at the USB connector) at 5 V, regardless of load conditions. Most portable devices charge at maximum current when 5 V is present at the USB connector. Figure 10-19 provides an example of resistor drops encountered when designing an automotive USB system with a remote USB connector location.

GUID-CD404163-9AB3-442C-830D-96808CC172EB-low.pngFigure 10-19 Automotive USB Resistances
GUID-9D25F8F9-174A-454A-AB25-2C7C2A59B966-low.gifFigure 10-20 Voltage Drop

The TPS2584x-Q1 detects the load current and increases the voltage at the CSN/OUT pin to compensate the IR drop in the charging path according to the gain set by the RSNS, RSET, and RIMON resistors as described in RSNS, RSET, RILIMIT, and RIMON.

The amount of cable droop compensation required can be estimated by the following equation: ΔVOUT = (RSNS + RDSON_NFET + RWIRE) IBUS× RIMON is then chosen by RIMON = (ΔVOUT × RSET × 2) / (IBUS × RSNS), Where ΔVOUT is the desired cable droop compensation voltage at full load.

In most cases, the recommended voltage across RSNS must be 50 mV. See the RSNS, RSET, RILIMIT, and RIMON section. In type-C application, typical RIMON resistors value are listed in Table 10-3 given the condition full load current = 3 A, RSNS = 15 mΩ and RSET = 300 Ω.

Table 10-3 Setting the Cable Compensation Voltage with RIMON
Cable Compensation Voltage at 3-A Full Load (V)RIMON (kΩ)
0.34.02
0.68.06
0.912.1
1.216.2
1.520
Note:

The maximum cable compensation voltage in TPS2584x-Q1 is 1.5 V.