SLVSEG3E September   2019  – March 2022 TPS25840-Q1 , TPS25842-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Buck Regulator
      2. 10.3.2  Enable/UVLO
      3. 10.3.3  Switching Frequency and Synchronization (RT/SYNC)
      4. 10.3.4  Spread-Spectrum Operation
      5. 10.3.5  VCC, VCC_UVLO
      6. 10.3.6  Minimum ON-time, Minimum OFF-time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Bootstrap Voltage (BOOT)
      9. 10.3.9  RSNS, RSET, RILIMIT and RIMON
      10. 10.3.10 Overcurrent and Short Circuit Protection
        1. 10.3.10.1 Current Limit Setting using RILIMIT
        2. 10.3.10.2 Buck Average Current Limit Design Example
        3. 10.3.10.3 External MOSFET Gate Drivers
        4. 10.3.10.4 Cycle-by-Cycle Buck Current Limit
      11. 10.3.11 Overvoltage, IEC and Short-to-Battery Protection
        1. 10.3.11.1 V BUS and V CSN/OUT Overvoltage Protection
        2. 10.3.11.2 DP_IN and DM_IN Protection
      12. 10.3.12 Cable Compensation
        1. 10.3.12.1 Cable Compensation Design Example
      13. 10.3.13 USB Port Control
      14. 10.3.14 FAULT Response
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 Device Power Pins (IN, CSN/OUT, and PGND)
      17. 10.3.17 Thermal Shutdown
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
      3. 10.4.3 Device Truth Table (TT)
      4. 10.4.4 USB Port Operating Modes
        1. 10.4.4.1 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
        2. 10.4.4.2 Charging Downstream Port (CDP) Mode
        3. 10.4.4.3 Client Mode
      5. 10.4.5 High-bandwidth Data-line Switches
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1  Output Voltage
        2. 11.2.2.2  Switching Frequency
        3. 11.2.2.3  Inductor Selection
        4. 11.2.2.4  Output Capacitor Selection
        5. 11.2.2.5  Input Capacitor Selection
        6. 11.2.2.6  Bootstrap Capacitor Selection
        7. 11.2.2.7  VCC Capacitor Selection
        8. 11.2.2.8  Enable and Under Voltage Lockout Set-Point
        9. 11.2.2.9  Current Limit Set-Point
        10. 11.2.2.10 Cable Compensation Set-Point
        11. 11.2.2.11 FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Ground Plane and Thermal Considerations
    3. 13.3 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 Support Resources
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.3.2 Enable/UVLO

The voltage on the EN/UVLO pin controls the ON or OFF operation of TPS2584x-Q1. An EN/UVLO pin voltage higher than VEN/UVLO-VOUT-H is required to start the internal regulator (Assume 5.1-k pull down resister on INT pin). The EN/UVLO pin is an input and can not be left open or floating. The simplest way to enable the operation of the TPS2584x-Q1 is to connect the EN to VIN. This action allows self-start-up of the TPS2584x-Q1 when VIN is within the operation range.

GUID-53A14160-C938-4C03-BD9E-C5B40BD80A34-low.gifFigure 10-2 Precision Enable Behavior

Many applications benefit from the employment of an enable divider RENT and RENB (Figure 10-3) to establish a precision system UVLO level for the TPS2584x-Q1. System UVLO can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery discharge level. To ensure the USB port VBUS is within the 5-V operating range as required for USB compliance (for the latest USB specifications and requirements, refer to USB.org), TI suggests that the RENT and RENB resistors be chosen such that the TPS2584x-Q1 enables when VIN is approximately 6 V. Considering the drop out voltage of the buck regulator and IR loses in the system, 6 V provides adequate margin to maintain VBUS within USB specifications. If system requirements such as a warm crank (start) automotive scenario require operation with VIN < 6 V, the values of RENT and RENB can be calculated assuming a lower VIN. An external logic signal can also be used to drive EN/UVLO input when a microcontroller is present and it is desirable to enable or disable the USB port remotely for other reasons.

GUID-89E6533F-20B3-4897-A1FA-F6064ED5C2B3-low.gifFigure 10-3 System UVLO by Enable Divider

UVLO configuration using external resistors is governed by the following equations:

Equation 1. GUID-A171A040-E467-4762-A1B8-C35E3BAEBF54-low.gif
Equation 2. GUID-CBEEB275-929D-4114-A9A0-3524C63581CC-low.gif

Example:

VIN(ON) = 6 V (user choice)

RENB = 5 kΩ (user choice)

RENT = [(VIN(ON) / VEN/UVLO_H) – 1] × RENB= 19.6 kΩ. Choose standard 20 kΩ.

Therefore, VIN(OFF) = 6 V × [1 – (0.09 V / 1.2 V)] = 5.55 V

A typical start-up waveform is shown in Figure 10-4. The rise time of DCDC VBUS voltage is about 5 ms.

GUID-39C2969D-A910-4E39-985F-A1558C4F5089-low.gifFigure 10-4 Typical Start-up Behavior, VIN = 13.5 V, RIMON = 12.6 kΩ

For TPS2584x-Q1, the pin voltage must meet the requirement below during startup. See Figure 10-5.

  • VBUS < 0.8 V (typical)
  • VDX_OUT < 2.2 V (typical)
  • VDX_IN < 1.5 V (typical)

After the 150-ms deglitch time, no additional requirement on these pins. In real application, BUCK_ST pin can be used to configure the timing sequence.

GUID-25522B1E-67C2-4AC3-9EAE-8DB4EBAB74EB-low.gif Figure 10-5 TPS2584x-Q1 Pin Voltage Requirement During Startup