SLVSFJ9 September   2021 TPS25854-Q1 , TPS25855-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Power Down or Undervoltage Lockout
      2. 10.3.2  Input Overvoltage Protection (OVP) - Continuously Monitored
      3. 10.3.3  Buck Converter
      4. 10.3.4  FREQ/SYNC
      5. 10.3.5  Bootstrap Voltage (BOOT)
      6. 10.3.6  Minimum ON-time, Minimum OFF-time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Current Limit and Short Circuit Protection
        1. 10.3.8.1 USB Switch Programmable Current Limit (ILIM)
        2. 10.3.8.2 Cycle-by-Cycle Buck Current Limit
        3. 10.3.8.3 OUT Current Limit
      9. 10.3.9  Cable Compensation
      10. 10.3.10 Thermal Management With Temperature Sensing (TS) and OTSD
      11. 10.3.11 Thermal Shutdown
      12. 10.3.12 FAULT Indication
      13. 10.3.13 USB Specification Overview
      14. 10.3.14 USB Type-C® Basics
        1. 10.3.14.1 Configuration Channel
        2. 10.3.14.2 Detecting a Connection
        3. 10.3.14.3 Plug Polarity Detection
      15. 10.3.15 USB Port Operating Modes
        1. 10.3.15.1 USB Type-C® Mode
        2. 10.3.15.2 Dedicated Charging Port (DCP) Mode
          1. 10.3.15.2.1 DCP BC1.2 and YD/T 1591-2009
          2. 10.3.15.2.2 DCP Divider-Charging Scheme
          3. 10.3.15.2.3 DCP 1.2-V Charging Scheme
        3. 10.3.15.3 DCP Auto Mode
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Output Voltage Setting
        2. 11.2.2.2 Switching Frequency
        3. 11.2.2.3 Inductor Selection
        4. 11.2.2.4 Output Capacitor Selection
        5. 11.2.2.5 Input Capacitor Selection
        6. 11.2.2.6 Bootstrap Capacitor Selection
        7. 11.2.2.7 Undervoltage Lockout Set-Point
        8. 11.2.2.8 Cable Compensation Set-Point
        9. 11.2.2.9 FAULT, POL, and THERM_WARN Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Ground Plane and Thermal Considerations
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 Support Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

GUID-2164F7C3-7BCA-4843-A1D3-954A5ABAE75C-low.png Figure 7-1 TPS2585x-Q1 RPQ Package25-Pin (QFN)Top View
Table 7-1 Pin Functions for TPS25854/5 RPQ Package
PIN TYPE (2) DESCRIPTION
NAME NO
NC 1, 12 A No connection
TS 2 A Temperature sense terminal. Connect the TS input to the NTC thermistor.
BIAS 3 P Input of internal bias supply, must connect to the SENSE pin directly, power the internal circuit.
DP 4 A D+ data line. Connect to the USB connector.
DM 5 A D– data line. Connect to the USB connector.
AGND 6 P Analog ground terminal. Connect AGND to PGND.
CC1 7 A Connect to Type-C CC1 pin. Analog input, output, or both.
CC2 8 A Connect to Type-C CC2 pin. Analog input, output, or both.
ILIM 9 A Current limit program. Connect a resistor to set the current limit threshold. Short to GND to set the default 3.55-A current limit.
BUS 10 P BUS Output
SENSE 11 P Output voltage sensing, external load on this pin is strictly prohibited. Connect to the other side of the external inductor.
OUT 13 P Output pin, provide 5.1-V voltage to power external load with maximum 200-mA capability. The voltage follows the VSENSE.
IMON 14 A USB output current monitor. Connect a resistor to set the maximum cable comp voltage at full load current.
THERM_WARN 15 A Thermal warning indication. Active LOW open-drain output. Asserted when voltage at the TS pin increases above the thermal warning threshold.
PGND 16, 24, 25 P Power ground terminal, connected to the source of LS FET internally. Connect to system ground, AGND, and the ground side of CIN and COUT capacitors. Path to CIN must be as short as possible.
POL 17 A Cable polarity indication. Active low open-drain logic output, signals which Type-C CC pin is connected to the CC line. This gives the information needed to mux the super speed lines. Asserted when the CC2 pin is connected to the CC line in cable.
FAULT 18 A Fault indication. Active low open-drain logic output, Asserted during overcurrent or overtemperature conditions.
FREQ/ SYNC 19 A Switching frequency program and external clock input. Connect a resistor from FREQ to GND to set the switching frequency.
EN/UV 20 A Enable pin. Precision enable controls the regulator switching action and type-C. Do not float. High = on, Low = off. Can be tied to SENSE directly. Precision enable input allows adjustable UVLO by external resistor divider if tied to IN pin.
BOOT 21 P Bootstrap capacitor connection. Internally, the BOOT is connected to the cathode of the booststrap diode. Connect the 0.1-μF bootstrap capacitor from SW to BOOT.
IN 22 P Input power. Connected to external DC supply. Expected range of bypass capacitors is 1 μF to 10 μF. Connect from IN to PGND. Withstand up to 36 V without damage, but operating is suspended if VIN is above the 26-V OVP threshold.
SW 23 P Switching output of the regulator. Internally connected to source of the HS FET and drain of the LS FET. Connect to output inductor.
(2) A = Analog, P = Power, G = Ground.