The TPS25921 is a compact, feature rich eFuse with a full suite of protection functions. The wide operating voltage allows control of many popular DC buses. The precise ±2% current limit, at room temperature, provides excellent accuracy making the TPS25921 well suited for many system protection applications.
Load, source and device protection are provided with multiple programmable features including overcurrent, overvoltage and undervoltage. 3% threshold accuracy for UV and OV, ensures tight supervision of bus voltages, eliminating the need for supervisor circuitry. Fault flag output (FLT) is provided for system status monitoring and down stream load control.
For hot-plug-in boards, TPS25921 provides in-rush current control and programmable output ramp-rate. Output ramp rate is programmable using a capacitor at soft-start (SS) pin, for maximum design flexibility.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS25921A | SOIC | 4.90mm x 3.91mm |
TPS25921L |
Changes from B Revision (August 2015) to C Revision
Changes from A Revision (March 2015) to B Revision
Changes from * Revision (August 2014) to A Revision
NAME | NUMBER | DESCRIPTION |
---|---|---|
GND | 1 | Ground. |
SS | 2 | A capacitor from this pin to GND sets the ramp rate of output voltage at device turn-on. |
ENUV | 3 | Input for setting programmable undervoltage lockout threshold. An undervoltage event will open internal FET and assert FLT to indicate power-failure. When pulled to GND, resets the thermal fault latch in TPS25921L. |
IN | 4 | Power Input and supply voltage of the device. |
OUT | 5 | Power Output of the device. |
FLT | 6 | Fault event indicator, goes low to indicate fault condition due to Undervoltage, Overvoltage, and Thermal shutdown event. A nuisance fast trip does not trigger fault. It is an open drain output. |
ILIM | 7 | A resistor from this pin to GND will set the overload and short circuit limit. |
OVP | 8 | Input for setting programmable overvoltage protection threshold. An overvoltage event will open the internal FET and assert FLT to indicate overvoltage. |
VALUE(2) | UNIT | |||
---|---|---|---|---|
MIN | MAX | |||
Input voltage range | IN, OUT, ENUV, OVP, FLT | –0.3 | 20 | V |
IN (10 ms Transient) | 22 | |||
ILIM, SS | –0.3 | 7 | ||
Sink current | SS | 5 | mA | |
FLT | 100 | mA | ||
Source current | ILIM, SS, FLT | Internally Limited | ||
Maximum junction temperature, TJ | Internally Limited | °C | ||
Storage temperature range, Tstg | -65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
Input voltage range | IN | 4.5 | 18 | V | |
OUT, OVP, ENUV, FLT | 0 | 18 | |||
SS | 0 | 6 | |||
ILIM | 0 | 3.3 | |||
Resistance | ILIM | 35.7 | 95.3 | 158 | kΩ |
External capacitance | OUT | 0.1 | 1 | µF | |
SS | 1 | 1000 | nF | ||
Operating junction temperature range, TJ | –40 | 25 | 125 | °C |
THERMAL METRIC | TPS2592xx | UNIT | |
---|---|---|---|
SOIC (8) PINS | |||
RθJA | Junction-to-ambient thermal resistance | 120.8 | °C/W |
RθJCtop | Junction-to-case (top) thermal resistance | 65.5 | |
RθJB | Junction-to-board thermal resistance | 51.8 | |
ψJT | Junction-to-top characterization parameter | 17.4 | |
ψJB | Junction-to-board characterization parameter | 61.2 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY VOLTAGE AND INTERNAL UNDERVOLTAGE LOCKOUT | ||||||
V(IN) | Operating Input Voltage | 4.5 | 18 | V | ||
V(UVR) | UVLO Threshold, Rising | 4.10 | 4.26 | 4.40 | V | |
V(UVHys) | UVLO Hysteresis | 168 | 224 | 279 | mV | |
IQ( ON) | Supply Current, Enabled | V(ENUV) = 2 V, V(IN) = 12 V | 0.22 | 0.41 | 0.58 | mA |
IQ( OFF) | Supply Current, Disabled | V(ENUV) = 0 V, V(IN) = 12 V | 0.08 | 0.132 | 0.20 | mA |
OVERVOLTAGE PROTECTION (OVP) INPUT | ||||||
V(OVPR) | Overvoltage Threshold Voltage, Rising | 1.35 | 1.39 | 1.43 | V | |
V(OVPF) | Overvoltage Threshold Voltage, Falling | 1.30 | 1.34 | 1.37 | V | |
I(OVP) | OVP Input Leakage Current | 0V ≤ V(OVP) ≤ 18 V | –100 | 0 | 100 | nA |
ENABLE AND UNDERVOLTAGE LOCKOUT (ENUV) INPUT | ||||||
V(ENR) | ENUV Threshold voltage, rising | 1.36 | 1.39 | 1.42 | V | |
V(ENF) | ENUV Threshold voltage, falling | 1.30 | 1.34 | 1.37 | V | |
V(ENF_RST) | ENUV Threshold voltage to reset thermal fault, falling | 0.5 | 0.61 | 0.8 | V | |
IEN | EN Input leakage current | 0 ≤ V(ENUV) ≤ 18 V | –100 | 0 | 100 | nA |
SOFT START: OUTPUT RAMP CONTROL (SS) | ||||||
I(SS) | SS charging current | V(SS) = 0 V | 0.9 | 1.04 | 1.2 | µA |
R(SS) | SS discharging resistance | V(ENUV) = 0 V, I(SS) = 10 mA sinking | 60 | 70 | 85 | Ω |
V(SSmax) | SS maximum capacitor voltage | 5.5 | V | |||
GAIN(SS) | SS to OUT gain | ΔV(OUT)/ΔV(SS) | 4.81 | 4.86 | 4.92 | V/V |
CURRENT LIMIT PROGRAMMING (ILIM) | ||||||
I(ILIM) | ILIM Bias current | 6 | 10 | 16 | µA | |
ILIMIT | Current Limit(2) | R(ILIM) = 35.7 kΩ, (V(IN) - V(OUT)) = 1 V | 0.284 | 0.368 | 0.452 | A |
R(ILIM) = 45.3 kΩ, (V(IN) - V(OUT)) = 1 V | 0.394 | 0.471 | 0.547 | |||
R(ILIM) = 95.3 kΩ, (V(IN) - V(OUT)) = 1 V, TA = TJ= 25°C | 0.98 | 1.0 | 1.02 | |||
R(ILIM) = 95.3 kΩ, (V(IN) - V(OUT)) = 1 V | 0.93 | 1.0 | 1.062 | |||
R(ILIM) = 150 kΩ, (V(IN) - V(OUT)) = 1 V | 1.43 | 1.57 | 1.7 | |||
R(ILIM) = SHORT, Shorted resistor current limit R(ILIM) = OPEN, Open resistor current limit (Single Point Failure Test: UL60950) |
0.12 | 0.257 | 0.406 | |||
IOS | Short-circuit current limit(2) | R(ILIM) = 35.7 kΩ, (V(IN) - V(OUT)) = 12 V | 0.275 | 0.356 | 0.438 | A |
R(ILIM) = 45.3 kΩ, (V(IN) - V(OUT)) = 12 V | 0.376 | 0.45 | 0.522 | |||
R(ILIM) = 95.3 kΩ, (V(IN) - V(OUT)) = 12 V | 0.837 | 0.9 | 0.964 | |||
R(ILIM) = 150 kΩ, (V(IN) - V(OUT)) = 12 V | 1.219 | 1.34 | 1.46 | |||
I(FASTRIP) | Fast-Trip comparator threshold | R(ILIM) in kΩ | 0.0142 x R(ILIM) + 0.36 | A | ||
V(ILIMopen) | ILIM Open resistor detect threshold | V(ILIM) Rising, R(ILIM) = OPEN | 2.81 | 3.0 | 3.25 | V |
MOSFET – POWER SWITCH | ||||||
RDS(on) |
FET ON resistance(1) |
–40°C ≤ TJ ≤ 85°C | 55 | 87 | 120 | mΩ |
–40°C ≤ TJ ≤ 125°C | 55 | 87 | 135 | |||
PASS FET OUTPUT (OUT) | ||||||
Ilkg(OUT) | OUT Bias current in off state | V(ENUV) = 0 V, V(OUT) = 0 V (Sourcing) | –2 | 0 | 1 | µA |
Isink(OUT) | V(ENUV) = 0V, V(OUT) = 300 mV (Sinking) | 5 | 7 | 10 | ||
FAULT FLAG (FLT): ACTIVE LOW | ||||||
R(FLT) | FLT Pull down Resistance | Device in fault condition, V(ENUV) = 0V, I(FLT) = 100mA | 22 | 26 | 32 | Ω |
I(FLT) | FLT Input Leakage Current | Device not in fault condition, V(FLT) = 0V, 18V | –0.5 | 0 | 0.5 | µA |
THERMAL SHUT DOWN (TSD) | ||||||
T(TSD) | TSD Threshold, rising(1) | 155 | °C | |||
T(TSDhys) | TSD Hysteresis(1) | 20 | °C | |||
Thermal fault: Latched or Auto Retry | TPS25921L | LATCHED | ||||
TPS25921A | AUTO-RETRY |
C(SS) = Open |
PD = [V(IN)-V(OUT)]*ILIMIT |
C(SS) = Open | C(OUT) = 4.7 nF |
R(FLT) = 100 kΩ |
RL = 12 Ω | R(FLT) = 100 kΩ |
Taken on 1-Layer board, 2oz.(0.08-mm thick) with GND plane area: 14 cm2 (bottom) |
C(SS) = 1nF | C(OUT) = 4.7 nF |
R(FLT) = 100 kΩ |
RL = 12 Ω | R(FLT) = 100 kΩ |