SLVSCV0B August   2015  – September 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 GND
      2. 8.3.2 VIN
      3. 8.3.3 dV/dT
      4. 8.3.4 BFET
      5. 8.3.5 EN/UVLO
      6. 8.3.6 ILIM
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Simple 3.7-A eFuse Protection for Set Top Boxes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Step by Step Design Procedure
          2. 9.2.1.2.2 Programming the Current-Limit Threshold: RILIM Selection
          3. 9.2.1.2.3 Undervoltage Lockout Set Point
          4. 9.2.1.2.4 Setting Output Voltage Ramp Time (TdVdT)
            1. 9.2.1.2.4.1 Case 1: Start-Up without Load: Only Output Capacitance COUT Draws Current During Start-Up
            2. 9.2.1.2.4.2 Case 2: Start-Up with Load: Output Capacitance COUT and Load Draws Current During Start-Up
          5. 9.2.1.2.5 Support Component Selection—CVIN
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Inrush and Reverse Current Protection for Hold-Up Capacitor Application (for example, SSD)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Programming the Current-Limit Threshold: RILIM Selection
          2. 9.2.2.2.2 Undervoltage Lockout Set Point
          3. 9.2.2.2.3 Setting Output Voltage Ramp Time (TdVdT)
          4. 9.2.2.2.4 Support Component Selection - CVIN
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Controlled Power Down using TPS25923x
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DRC Package
10-Pin VSON
Top View
TPS259230 TPS259231 pin_out_top_SLVSC11.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BFET 9 O Connect this pin to the gate of a blocking NFET. See the Feature Description section. Leave this pin floating if it is not used
dV/dT 1 O Tie a capacitor from this pin to GND to control the ramp rate of OUT at device turnon
EN/UVLO 2 I This is a dual function control pin. When used as an ENABLE pin and pulled down, it shuts off the internal pass MOSFET and pulls BFET to GND. When pulled high, it enables the device and BFET.
As an UVLO pin, it can be used to program different UVLO trip point via external resistor divider
GND Thermal Pad — GND
ILIM 10 O A resistor from this pin to GND sets the overload and short circuit limit
OUT 6-8 O Output of the device
VIN 3-5 I Input supply voltage