SLVSC11C June   2013  – December 2014 TPS2592AA , TPS2592AL

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Application Schematic
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 GND
      2. 9.3.2 VIN
      3. 9.3.3 dV/dT
      4. 9.3.4 BFET
      5. 9.3.5 EN/UVLO
      6. 9.3.6 ILIM
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Simple 3.7-A eFuse Protection for Set Top Boxes
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Step by Step Design Procedure
          2. 10.2.1.2.2 Programming the Current-Limit Threshold: RILIM Selection
          3. 10.2.1.2.3 Undervoltage Lockout Set Point
          4. 10.2.1.2.4 Setting Output Voltage Ramp Time (TdVdT)
            1. 10.2.1.2.4.1 Case 1: Start-up without Load: Only Output Capacitance COUT Draws Current During Start-up
            2. 10.2.1.2.4.2 Case 2: Start-up with Load: Output Capacitance COUT and Load Draws Current During Start-up
        3. 10.2.1.3 Support Component Selection - CVIN
        4. 10.2.1.4 Application Curves
      2. 10.2.2 Inrush and Reverse Current Protection for Hold-Up Capacitor Application (e.g., SSD)
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Programming the Current-Limit Threshold: RILIM Selection
          2. 10.2.2.2.2 Undervoltage Lockout Set Point
          3. 10.2.2.2.3 Setting Output Voltage Ramp Time (TdVdT)
        3. 10.2.2.3 Application Curves
    3. 10.3 Maximum Device Power Dissipation Considerations
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
    2. 11.2 Output Short-Circuit Measurements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

10-Pin VSON
DRC Package
(Top View)
TPS2592AA TPS2592AL pin_out_top_SLVSC11.gif

Pin Functions

PIN DESCRIPTION
NAME NUMBER
BFET 9 Connect this pin to the gate of a blocking NFET. See the Feature Description.
dV/dT 1 Tie a capacitor from this pin to GND to control the ramp rate of OUT at device turn-on.
EN/UVLO 2 This is a dual function control pin. When used as an ENABLE pin and pulled down, it shuts off the internal pass MOSFET and pulls BFET to GND. When pulled high, it enables the device and BFET.
As an UVLO pin, it can be used to program different UVLO trip point via external resistor divider.
GND PowerPAD™ GND
ILIM 10 A resistor from this pin to GND will set the overload and short circuit limit.
OUT 6-8 Output of the device
VIN 3-5 Input supply voltage