SLVSDJ0E May   2016  – January 2021 TPS25940-Q1

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parametric Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable and Adjusting Undervoltage Lockout
      2. 9.3.2 Overvoltage Protection (OVP)
      3. 9.3.3 Hot Plug-In and In-Rush Current Control
      4. 9.3.4 Overload and Short Circuit Protection
        1. 9.3.4.1 Overload Protection
        2. 9.3.4.2 Short Circuit Protection
        3. 9.3.4.3 Start-Up with Short on Output
        4. 9.3.4.4 Constant Current Limit Behavior During Overcurrent Faults
      5. 9.3.5 FAULT Response
      6. 9.3.6 Current Monitoring
      7. 9.3.7 Power Good Comparator
      8. 9.3.8 IN, OUT and GND Pins
      9. 9.3.9 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 DevSleep Mode
      2. 9.4.2 Shutdown Control
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Step by Step Design Procedure
        2. 10.2.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
        3. 10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
        4. 10.2.2.4 Programming Current Monitoring Resistor—RIMON
        5. 10.2.2.5 Setting Output Voltage Ramp Time (tdVdT)
          1. 10.2.2.5.1 Case1: Start-Up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-Up
          2. 10.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-Up
        6. 10.2.2.6 Programing the Power Good Set Point
        7. 10.2.2.7 Support Component Selections—R6, R7 and CIN
      3. 10.2.3 Application Curves
      4. 10.2.4 System Examples
        1. 10.2.4.1 VBUS Short-to-Battery, Short-to-Ground Protection of USB Port in Automotive Systems
        2. 10.2.4.2 Power Failure Protection for Holdup Power
        3. 10.2.4.3 Overload Detection Using TPS25940xx-Q1
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
    2. 11.2 Output Short-Circuit Measurements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Timing Requirements

–40°C ≤ TJ = TA ≤ 125°C, 2.7 V ≤ V(IN) = 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DEVSLP) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise noted). See Figure 8-1 for the timing diagrams.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ENABLE and UVLO INPUT
tON(dly)EN turnon delayEN/UVLO ↑ (100 mV above V(ENR)) to V(OUT) = 100 mV,
C(dVdT) < 0.8 nF		220µs
EN/UVLO ↑ (100 mV above V(ENR)) to V(OUT) = 100 mV,
C(dVdT) ≥ 0.8 nF, [C(dVdT) in nF]		100 + 150 × C(dVdT)µs
tOFF(dly)EN turnoff delayEN/UVLO ↓ (100 mV below V(ENF)) to FLT↓2µs
OVERVOLTAGE PROTECTION INPUT (OVP)
tOVP(dly)OVP disable delayOVP↑ (100 mV above V(OVPR)) to FLT↓2µs
OUTPUT RAMP CONTROL (dV/dT )
tdVdTOutput ramp timeEN/UVLO ↑ to V(OUT) = 4.5 V, with C(dVdT) = open0.12ms
EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = open0.250.370.5
EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = 1 nF0.97
CURRENT LIMIT
tFASTRIP(dly)Fast-trip comparator delayI(OUT) > I(FASTRIP)200ns
REVERSE PROTECTION COMPARATOR
tREV(dly)Reverse protection comparator delay(V(IN) – V(OUT))↓ (1 mV overdrive below V(REVTH)) to FLT↓10µs
(V(IN) – V(OUT))↓ (10 mV overdrive below V(REVTH)) to FLT↓1
tFWD(dly)(V(IN) – V(OUT))↑ (10 mV overdrive above V(FWDTH)) to FLT↑3.1
POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH
tPGOODRPGOOD delay (de-glitch) timeRising edge0.420.540.66ms
tPGOODFFalling edge0.420.540.66ms
THERMAL SHUT DOWN (TSD)
Retry delay in TSDTPS25940-Q1/TPS259401A-Q1 Only128ms