Table 1. Design Parameters

10.2.1.2.1 Step by Step Design Procedure

To begin the design process a few parameters must be decided upon. The designer needs to know the following:

• Normal input operation voltage
• Maximum output capacitance
• Maximum current Limit
• Load during start-up
• Maximum ambient temperature of operation

This design procedure below seeks to control the junction temperature of device under both static and transient conditions by proper selection of output ramp-up time and associated support components. The designer can adjust this procedure to fit the application and design criteria.

10.2.1.2.2 Programming the Current-Limit Threshold: R_(ILIM) Selection

The R_(ILIM) resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.

Equation 9.

Choose closest standard value: 17.8k, 1% standard value resistor.

10.2.1.2.3 Undervoltage Lockout and Overvoltage Set Point

The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using the external voltage divider network of R₁, R₂ and R₃ as connected between IN, EN, OVP and GND pins of the device. The values required for setting the undervoltage and overvoltage are calculated solving Equation 10 and Equation 11.

Equation 10.

Equation 11.

For minimizing the input current drawn from the power supply {I_(R123) = V_(IN)/(R₁ + R₂ + R₃)}, it is recommended to use higher values of resistance for R₁, R₂ and R₃.

However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, I_(R123) must be chosen to be 20x greater than the leakage current expected.

From the device electrical specifications, V_(OVPR) = 0.99 V and V_(ENR) = 0.99 V. For design requirements, V_(OV) is 16.5 V and V_(UV) is 10.8 V. To solve the equation, first choose the value of R₃ = 31.2 kΩ and use Equation 10 to solve for (R₁ + R₂) = 488.8 kΩ. Use Equation 11 and value of (R₁ + R₂) to solve for R₂ = 16.47 kΩ and finally R₁= 472.33 kΩ.

Using the closest standard 1% resistor values gives R₁ = 475 kΩ, R₂ = 16.7 kΩ, and R₃ = 31.2 kΩ.

The power failure threshold is detected on the falling edge of supply. This threshold voltage is 7% lower than the rising threshold, V_(UV). This is calculated using Equation 12.

10.2.1.2.4 Programming Current Monitoring Resistor - R_IMON

Voltage at IMON pin V_(IMON) represents the voltage proportional to load current. This can be connected to an ADC of the downstream system for health monitoring of the system. The R_(IMON) need to be configured based on the maximum input voltage range of the ADC used. R_(IMON) is set using Equation 13.

Equation 13.

For I_(LIM) = 5 A, and considering the operating range of ADC from 0 V to 5 V, V_(IMONmax) is 5 V and R_(IMON) is determined by:

Equation 14.

Selecting R_(IMON) value less than determined by Equation 14 ensures that ADC limits are not exceeded for maximum value of load current.

If the IMON pin voltage is not being digitized with an ADC, R_(IMON) can be selected to produce a 1V/1A voltage at the IMON pin, using Equation 13.

Choose closest 1 % standard value: 19.1 kΩ.

If current monitoring up to I_(FASTRIP) is desired, R_(IMON) can be reduced by a factor of 1.6, as in Equation 5.

10.2.1.2.5 Setting Output Voltage Ramp time (t_dVdT)

For a successful design, the junction temperature of device should be kept below the absolute-maximum rating during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.

The ramp-up capacitor C_(dVdT) needed is calculated considering the two possible cases:

10.2.1.2.5.1 Case1: Start-up Without Load: Only Output Capacitance C_(OUT) Draws Current During Start-up

During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and the power dissipated decreases as well. Typical ramp-up of output voltage V_(OUT) with inrush current limit of 1.2A and power dissipated in the device during start-up is shown in Figure 53. The average power dissipated in the device during start-up is equal to area of triangular plot (red curve in Figure 54) averaged over t_dVdT.

V(IN) = 12 V

C(dVdT) = 1 nF

C(OUT)=100 µF

Figure 53. Start-up Without Load

V(IN) = 12 V

C(dVdT) = 1 nF

C(OUT)=100 µF

Figure 54. P_D(INRUSH) Due to Inrush Current

For TPS25940 device, the inrush current is determined as,

Equation 15.

Power dissipation during start-up is:

Equation 16.

Equation 16 assumes that load does not draw any current until the output voltage has reached its final value.

10.2.1.2.5.2 Case 2: Start-up With Load: Output Capacitance C_(OUT) and Load Draws Current During Start-up

When load draws current during the turn-on sequence, there will be additional power dissipated. Considering a resistive load R_L(SU) during start-up, load current ramps up proportionally with increase in output voltage during t_dVdT time. Typical ramp-up of output voltage, Load current and power dissipation in the device is shown in Figure 55 and power dissipation with respect to time is plotted in Figure 56. The additional power dissipation during start-up phase is calculated as follows.

Equation 17.

Equation 18.

Where R_L(SU) is the load resistance present during start-up. Average energy loss in the internal FET during charging time due to resistive load is given by:

Equation 19.

V(IN) = 12 V

C(dVdT) = 1 nF

RL(SU) = 4.8 Ω

Figure 55. Start-up With Load

V(IN) = 12 V

C(dVdT) = 1 nF

RL(SU) = 4.8 Ω

Figure 56. P_D(LOAD) in Load During Start-up

On solving Equation 19 the average power loss in the internal FET due to load is:

Equation 20.

Total power dissipated in the device during startup is:

Equation 21.

Total current during startup is given by:

Equation 22.

If I_(STARTUP) > I_(LIM), the device limits the current to I_(LIM) and the current limited charging time is determined by:

Equation 23.

The power dissipation, with and without load, for selected start-up time should not exceed the shutdown limits as shown in Figure 57.

Taken on 2-Layer board, 2oz.(0.08-mm thick) with GND plane area: 14 cm2 (Top) and 20 cm2 (bottom)

Figure 57. Thermal Shutdown Limit Plot

For the design example under discussion,

Select ramp-up capacitor C_(dVdT) = 1nF, using Equation 2.

Equation 24.

The inrush current drawn by the load capacitance (C_(OUT)) during ramp-up using Equation 3.

Equation 25.

The inrush Power dissipation is calculated, using Equation 16.

Equation 26.

For 7.2 W of power loss, the thermal shut down time of the device should not be less than the ramp-up time t_dVdT to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 57 at T_A = 85°C, for 7.2 W of power the shutdown time is ~60 ms. So it is safe to use 1 ms as start-up time without any load on output.

Considering the start-up with load 4.8 Ω, the additional power dissipation, when load is present during start up is calculated, using Equation 20.

Equation 27.

The total device power dissipation during start up is:

Equation 28.

From thermal shutdown limit graph at T_A = 85°C, the thermal shutdown time for 12.2 W is close to 7.5 ms. It is safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and input voltage. So it is well within acceptable limits to use the 1 nF capacitor with start-up load of 4.8 Ω.

If there is a need to decrease the power loss during start-up, it can be done with increase of C_(dVdT) capacitor.

To illustrate, choose C_(dVdT) = 1.5 nF as an option and recalculate:

Equation 29.

Equation 30.

Equation 31.

Equation 32.

Equation 33.

From thermal shutdown limit graph at T_A = 85°C, the shutdown time for 10 W power dissipation is ~17 ms, which increases the margins further for shutdown time and ensures successful operation during start up and steady state conditions.

The spreadsheet tool available on the web can be used for iterative calculations.

10.2.1.2.6 Programing the Power Good Set Point

As shown in Figure 52, R₄ and R₅ sets the required limit for PGOOD signal as needed for the downstream converters. Considering a power good threshold of 11 V for this design, the values of R₄ and R₅ are calculated using Equation 34.

Equation 34.

It is recommended to have high values for these resistors to limit the current drawn from the output node. Choosing a value of R₄ = 475 kΩ, R₅ = 47 kΩ provides V_(PGTH) = 11 V.

10.2.1.2.7 Support Component Selections - R₆, R₇ and C_IN

Reference to application schematics, R₆ and R₇ are required only if PGOOD and FLT are used; these resistors serve as pull-ups for the open-drain output drivers. The current sunk by each of these pins should not exceed 10 mA (refer to the Absolute Maximum Ratings table). C_IN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for C_(IN).