9.3.1 Enable and Adjusting Undervoltage Lockout

The EN/UVLO pin controls the ON/OFF state of the internal FET. A voltage V_(EN/UVLO) < V_(ENF) on this pin will turn off the internal FET, thus disconnecting IN from OUT, while voltage below V_(SHUTF) will take the device into shutdown mode, with I_Q less than 15 µA to ensure minimal power loss. Cycling EN/UVLO low and then back high resets the TPS25940L that has latched off due to a fault condition.

The internal de-glitch delay on EN/UVLO falling edge is kept low for quick detection of power failure. For applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO terminal to GND.

The undervoltage lock out can be programmed by using an external resistor divider from supply IN terminal to EN/UVLO terminal to GND as shown in Figure 44. When an undervoltage or input power fail event is detected, the internal FET is quickly turned off, and FLT is asserted. If the Under-Voltage Lock-Out function is not needed, the EN/UVLO terminal should be connected to the IN terminal. EN/UVLO terminal should not be left floating.

The device also implements internal undervoltage-lockout (UVLO) circuitry on the IN terminal. The device disables when the IN terminal voltage falls below internal UVLO Threshold V_(UVF). The internal UVLO threshold has a hysteresis of 115mV.

Figure 44. UVLO and OVP Thresholds Set By R₁, R₂ and R₃

9.3.2 Overvoltage Protection (OVP)

The device incorporates circuit to protect system during overvoltage conditions. A resistor divider connected from the supply to OVP terminal to GND (as shown in Figure 44) programs the overvoltage threshold. A voltage more than V_(OVPR) on OVP pin turns off the internal FET and protects the downstream load. This pin should be tied to GND when not used.

9.3.3 Hot Plug-in and In-Rush Current Control

The device is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot" power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets of the system power. A slew rate controlled startup (dVdT) also helps to eliminate conductive and radiative interferences. An external capacitor connected from the dVdT pin to GND defines the slew rate of the output voltage at power-on (as shown in Figure 45). Equation governing slew rate at start-up is shown in Equation 1 :

Figure 45. Output Ramp Up Time t_dVdT is Set by C_(dVdT)

Equation 1.

Where:

• I_(dVdT) = 1 µA (typical)
• = Desired output slew rate
• GAIN_(dVdT) = dVdT to OUT gain = 12

The total ramp time (t_dVdT) of V_(OUT) for 0 to V_(IN) can be calculated using Equation 2:

The inrush current, I_(INRUSH) can be calculated as

The dVdT pin can be left floating to obtain a predetermined slew rate (t_dVdT) on the output. When terminal is left floating, the device sets an internal ramp rate of 12V/ms for output (V_(OUT)) ramp.

Figure 58 and Figure 59 illustrate the inrush current control behavior of the device. For systems where load is present during start-up, the current never exceeds the overcurrent limit set by R_(ILIM) resistor for the application. For defining appropriate charging time/rate under different load conditions, refer to the Setting Output Voltage Ramp time (tdVdT) section.

9.3.4 Overload and Short Circuit Protection :

At all times load current is monitored by sensing voltage across an internal sense resistor. During overload events, current is limited to the current limit (I_(LIM)) programmed by R_(ILIM) resistor

Equation 4.

• I_(LIM) is overload current limit in Ampere
• R_(ILIM) is the current limit resistor in kΩ

The device incorporates two distinct levels: a current limit (I_(LIM)) and a fast-trip threshold (I_(FASTRIP)). Fast trip and current limit operation are shown in Figure 46.

Bias current on ILIM pin directly controls current-limiting behavior of the device, and PCB routing of this node must be kept away from any noisy (switching) signals.

9.3.4.4 Constant Current Limit Behavior During Overcurrent Faults

When power dissipation in the internal FET [P_D = (V_(IN) - V_(OUT)) × I_(OUT)] > 10 W, there is a ~0 to 5 % thermal fold back in the current limit value so that I_(LIM) drops to I_OS. Eventually, the device shuts down due to over temperature.

Figure 46. Fast-Trip Current

9.3.5 FAULT Response

The FLT open-drain output is asserted (active low) during undervoltage, overvoltage, reverse voltage/current and thermal shutdown conditions. The FLT signal remains asserted until the fault condition is removed and the device resumes normal operation. The device is designed to eliminate false fault reporting by using an internal "de-glitch" circuit for undervoltage and overvoltage (2.2-µs typical) conditions without the need for external circuitry. This ensures that fault is not accidentally asserted during transients on input bus.

Connect FLT with a pull up resistor to Input or Output voltage rail. FLT may be left open or tied to ground when not used. V_(IN) falling below V_(UVF) = 2.1 V resets FLT.

9.3.6 Current Monitoring:

The current source at IMON terminal is configured to be proportional to the current flowing from IN to OUT. This current can be converted to a voltage using a resistor R_(IMON) from IMON terminal to GND terminal. This voltage, computed using Equation 6, can be used as a means of monitoring current flow through the system.

The maximum voltage range for monitoring the current (V_(IMONmax)) is limited to minimum([V_(IN)- 2.2 V], 6.0 V) to ensure linear output. This puts limitation on maximum value of R_(IMON) resistor and is determined by Equation 5.

Equation 5.

The output voltage at IMON terminal is calculated from Equation 6.

Equation 6.

Where

• GAIN_(IMON) = Gain factor I_(IMON):I_(OUT) = 52 µA/A
• I_(OUT) = Load current
• I_{(IMON_OS)} = 0.8 µA (typ)

This pin should not have a bypass capacitor to avoid delay in the current monitoring information.

The voltage at IMON pin can be digitized using an ADC (such as ADS1100, SBAS239) to read the current monitor information over an I2C bus.

9.3.7 Power Good Comparator

The device incorporates a Power Good comparator for co-ordination of status to downstream DC-DC converters or system monitoring circuits. The comparator has an internal reference of V_(PGTHR) = 0.99 V at negative terminal and positive terminal PGTH can be utilized for monitoring of either input or output of the device. The comparator output PGOOD is an open-drain active high signal, which can be used to indicate the status to downstream units. PGOOD is asserted high when internal FET is fully enhanced and PGTH pin voltage is higher than internal reference V_(PGTHR).

The PGOOD signal has deglitch time incorporated to ensure that internal FET is fully enhanced before heavy load is applied by downstream converters. Rising de-glitch delay is determined by Equation 7.

Connect the PGOOD pin with a pull up resistor to Input or Output voltage rail. PGOOD may be left open or tied to ground when not used.

9.3.8 IN, OUT and GND Pins

The device has multiple pins for input (IN) and output (OUT).

All IN pins should be connected together and to the power source. A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus transients. The recommended operating voltage range is 2.7 V – 18 V.

Similarly all OUT pins should be connected together and to the load. V_(OUT) in the ON condition, is calculated using the Equation 8

Equation 8.

where, R_ON is the total ON resistance of the internal FET.

GND terminal is the most negative voltage in the circuit and is used as a reference for all voltage reference unless otherwise specified.

9.3.9 Thermal Shutdown:

Internal over temperature shutdown disables turns off the FET when T_J > 160°C (typical). The TPS25940L version latches off the internal FET, whereas TPS25940A commences an auto-retry cycle128 ms after T_J drops below [T_(TSD) - 12°C]. During the thermal shutdown, the fault pin FLT pulls low to signal a fault condition.

9.4.1 DevSleep Mode for SATA® Interface Devices

DevSleep is a new state introduced in the SATA® specification, which requires SATA-based storage solutions to reach a level of low power operation. This is appended to meet the aggressive power/battery life requirements of SATA-based mobile devices. DevSleep enables hosts and devices to completely hibernate the SATA interface. This saves more power versus the existing Partial and Slumber interface power states, which require that the PHY be left powered. In this mode, power consumption is limited to 5 mW or less for SSDs.

Detailed information on DevSleep is available in document 'SATA-DevSleep' and on www.sata-io.org

TPS25940 provides a dedicated DevSleep interface terminal (DEVSLP) to drive the device in low power mode. The DEVSLP terminal is compatible with standard hardware signals asserted from the host controller. When pulled high, it puts the device in low power DevSleep mode. In this mode, the quiescent current consumption of the device is limited to less than 130 µA (95 µA typical). During this mode, the output voltage remains active, the overload current limit is set to I_{(DEVSLP(LIM))} and functionality of reverse comparator and current monitoring is disabled. All other protections are kept active ensuring the safety of the system even in DevSleep mode.

User must ensure that load currents on the bus are limited to less than I_{(DEVSLP(LIM))}, when the device is driven to DevSleep mode. Also, while coming out of DevSleep, it is important to sequence the TPS25940 earlier than the load. Otherwise, the load can exceed I_{(DEVSLP(LIM))} and cause TPS25940 to enter the overload mode.

Figure 47 through Figure 50 illustrate the behavior of the system in DevSleep mode.

V(IN) = 12 V	l(LIM) = 5.3A	RL = 22Ω
C(OUT) = 1 µF

Figure 47. IN and OUT of DevSleep Mode with 550 mA Load

RL = 22Ω	l(LIM) = 5.3A	C(OUT) = 1 µF

Figure 49. IMON Disabled in DevSleep Mode

V(IN) = 12 V	l(LIM) = 5.3A	RL = 15Ω
C(OUT) = 1 µF

Figure 48. IN and OUT of DevSleep Mode with 800 mA Load. In DevSleep, Load Current gets Limited to I_{(DEVSLP(LIM))}

	l(LIM–) = 5.3A	C(OUT) = 1 µF

Figure 50. Hot Short and Retry in DevSleep Mode

9.4.2 Shutdown Control

The internal FET and hence the load current can be remotely switched off by taking the UVLO pin below its 0.6 V threshold with an open collector or open drain device as shown in Figure 51. The device quiescent current is reduced to less than 20 µA in this state. Upon releasing the UVLO pin the device turns on with soft-start cycle.

Figure 51. Shutdown Control